3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and 

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3D-IC technology has gone from the “grandiose plans” of several years ago to the “practical issues” of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS)

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Manufactured using GLOBALFOUNDRIES' leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the

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April 26, 2013 - 9:52amQ3D Notes created the posting More than Moore and 3D IC: Decoding the Code at the GSA Silicon Summit 2013

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GlobalFoundries Successfully Implements TSVs onto 20nm Manufacturing Process

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3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many

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April 1, 2013 - 3:53pmFrancoise Von Trapp created the posting For Discussion: Is Wright’s Law a better Economic Index for 3D ICs than Moore’s Law?

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The TSMC 2013 Technology Symposium, held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies.

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The new facilities are part of ASE's plans to enhance its manufacturing and R&D capabilities for advanced technologies, including bumping, copper pillar, TSV, flip chip and 3D IC packaging. Tweet. Categories: Bits + chips IC

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3D-IC designs are widely recognized as the next step towards meeting the growing performance requirements such as increased bandwidth, reduced latency, and lower power. 2.5D silicon interposers, which are

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Dr. Rajendran and Dr. Lim are two of the leading scientists in 3D IC field. San Jose, CA (PRWEB) April 03, 2013. MonolithIC 3D Inc., a Silicon Valley leading 3D-IC start-up, announced the formation and appointment of two

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Globalfoundries broke a huge milestone in the quest to 3D stacking of chips, a method that will speed up communications between layered chips

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System-to-Silicon (S2S) Verification Solution, 3D-IC Design Solutions · Technical Platforms Integrated product .... The primary drivers to greater NAND flash are the increasing demands of Smart Phone and Tablet users to run more apps, store more high resolution pictures (like the 13MP camera on the Samsung Galaxy S4) and eventually, in the future, those using the 4k video cameras supported by sensors by companies like Aptina. Go ahead do a search on 4k and

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April 10, 2013 - 4:27pmFrancoise Von Trapp created the posting 2.5D Products and 3DIC Standards and Roadmaps Are On the Move

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April 8, 2013 - 11:04amQ3D Notes created the event GSA 3D IC Working Group Meeting

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With the 2.5D/3D IC process technologies gradually being accepted by industry, IME has been actively engaging companies from the supply chain to drive the mass production of 2.5D/3D ICs. "IME's strong commitment in

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We may not see 3D chip stacks for next-gen smartphones until 2015 or later. We can, however, expect new chip designs for tablets using the much simpler 2.5D stacking techniques by late next year. The good and bad news

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Global Foundries has demonstrated its first functional 20 nm silicon wafers with integrated Through-Silicon Vias (TSVs) and reached a key milestone in the company's plan to enable 3D stacking of chips for next generation

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April 3, 2013 - 4:22pmFrancoise Von Trapp created the event NCCAVS Joint User Group Meeting: 3D Packaging

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April 3, 2013 - 2:30amGilbert Lecarpentier commented on 3D IC Reality Check saying Thank you Françoise, very

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April 2, 2013 - 3:05pmJayna Sheats commented on For Discussion: Is Wright’s Law a better Economic Index for 3D ICs than Moore’s Law? saying As a (former) chemist, I am

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As if Samsung didn’t have enough to worry about with their new neighbor to the North (Korea) declaring war on them, Samsung 28nm is still NOT yielding. In my previous blog “Can Samsung Deliver as Promised?” I wondered what will power the new Galaxy S4 phones that Samsung has been over marketing. You would think it would be a 28nm version of the Exynos 5 Octa SoC that was launched at CES in January with former President Bill Clinton. As it turns out that is not the case, which of course pleases me to no end. I like honesty, I like transparency, I don't like Samsung

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Imagination Technologies and contract chipmaker Taiwan Semiconductor Manufacturing Company (TSMC) have announced the next phase of their technology collaboration

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March 25, 2013 - 4:25pmFrancoise Von Trapp created the posting Easing the 3D IC Pain at IMAPS DPC 2013

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If I had a nickel for every time I heard the term “FinFET” at the 2013 SNUG (Synopsys User Group) Conference I could buy a dozen Venti Carmel Frappuccinos at Starbucks (my daughter’s favorite treat). In the keynote, Aart de Geus said FinFET 14 times and posed the question: Will FinFETs Yield at 14nm? So that was my mission, ask everybody I see if FinFETs will yield at 14nm

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Startup now has 26 issued patents and 4 to be issued soon in the field of monolithic 3D IC. San Jose, CA (PRWEB) March 13, 2013. MonolithIC 3D Inc., a Silicon Valley startup, announced today that it has been granted its

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Technology News. March 01, 2013 // Julien Happich. Developing and strengthening 3D IC manufacture in Europe. The European 3D TSV Summit that took place at Grenoble's Minatec campus late February gathered 320

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A look at the challenges and solutions for verifying and testing IC designs targeted for 2.5D or 3D packages

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United Microelectronics Corporation and STATS ChipPAC announced recently that their first 3D TSV-enabled IC Chip Stacking project was successfully completed. The chip also passed their first stage reliability testing

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STATS ChipPAC and UMC today announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration

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One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing

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While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior

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Startup now has 26 issued patents and 4 to be issued soon in the field of monolithic 3D IC. San Jose, CA (PRWEB) MonolithIC 3D Inc., a Silicon Valley startup, announced today that it has been granted its 30th patent on

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We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC. For those who could not make it, here is what our booth looked like: Picture. Nice tie

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Yes, unless we Augment Dimensional Scaling with monolithic 3D-IC Scaling. Picture. We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Cost Reduction

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The most common form of 3d technology involves through silicon vias, but a startup company called Monolithic 3d has an alternate approach. In an interview with Sander Olson for Next Big Future, Monolithic CEO Zvi Or-Bach

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In contrast, MonolithIC 3D proposes true 3-D design integration, in which the layers of a stack are designed as a single unit. Partitioning the design appropriately allows global interconnects to be vertical as well as horizontal,

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United Microelectronics Corporation and STATS ChipPAC announced recently that their first 3D TSV-enabled IC Chip Stacking project was successfully completed. The chip also passed their first stage reliability testing

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The impact of TSV proximity on this advanced CMOS remains a major concern . The difference in thermal expansion between the TSV metal and the Si substrate causes mechanical stresses in the silicon that may affect carrier

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March 13, 2013 - 7:55amEV Group Admin created the posting EV Group Ships 300-mm Wafer Bonding System to Leading Chinese Semiconductor Foundry for 3D IC and Advanced Packaging Volume Production Applications

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March 7, 2013 - 11:08amQ3D Notes created the posting Viewing 3D IC Blossoms at SPIE Advanced Lithography 2013

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February 27, 2013 - 4:40pmFrancoise Von Trapp created the posting 2013 Predictions for 3D ICs as reported by SPN

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February 22, 2013 - 1:40pmFrancoise Von Trapp created the posting 3D IC Blogosphere Update – Feb 22, 2013

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The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively

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"The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner's robust, leading-edge TSV and front-end-of-line (FEOL) process

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Is it viable for TSV production? TAIKO is a process where a thick wafer is thinned in the center to allow backside development. The semiconductor industry is facing a major challenge to increase the speed of certain core

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TechNavio's analysts forecast the Global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. One of the key factors contributing to this market growth is the huge demand for memory-enhanced

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Package-level reliability success is a significant milestone towards the prove-out of a full-scale 3D IC solution for customers HSINCHU, Jan. 29,

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The impact of TSV proximity on this advanced CMOS remains a major concern . The difference in thermal expansion between the TSV metal and the Si substrate causes mechanical stresses in the silicon that may affect carrier

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February 13, 2013 - 5:00pmQ3D Notes created the posting 3D IC Gets a Nod or Two of Encouragement at Common Platform Tech Forum 2013

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February 13, 2013 - 11:59amFrancoise Von Trapp created the event IPC APEX: Exploratory Strategy Meeting on 3D Packaging

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February 4, 2013 - 12:33pmFrancoise Von Trapp created the posting Proof that a Collaboration Model Works for 3D ICs

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January 17, 2013 - 3:37pmMartijn Pierik commented on 2013 Predictions for 3D ICs as told by Everyone - Part 1 saying Regarding #2 No other

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STATS ChipPAC and UMC today announced the world's first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration

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Successful three-dimensional integrated circuits (3D-ICs) use co-design techniques that perform thermal analyses not just of each individual die, but of all the dice in a 3-D die-stack, its packaging, the printed circuit board

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Altera Corp. and the Taiwan Semiconductor Manufacturing Company (TSMC) have jointly developed the world's first heterogeneous 3D IC test vehicle using TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process

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Imec and PVA Tepla present breakthrough results in the detection of TSV voids in 3D stacked IC technology. After having applied Scanning Acoustic Microscopy to temporary wafer (de)bonding inspection, they successfully

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[...]

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January 31, 2013 - 11:28amFrancoise Von Trapp created the posting European 3D TSV Summit Interview: Gilles Fresquet

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January 30, 2013 - 11:09amFrancoise Von Trapp created the posting European 3D TSV Summit: Focus on Cost of Ownership

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STATS ChipPAC and United Microelectronics Corporation (UMC) have jointly announced the first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration

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Network with Cadence technologists and peers in the Cadence Community. Stay abreast of technology trends, news and opinion through Blogs, forums, and social networking

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January 29, 2013 - 11:24amFrancoise Von Trapp created the posting 3D ICs News in Brief

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January 28, 2013 - 2:06pmFrancoise Von Trapp created the video/podcast Scenes from the European 3D TSV Summit 2013

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S2C Inc. today announced the addition of the newest prototyping platform, Quad V7, to its V7 TAI Logic Module series, a new generation of SoC/ASIC prototyping hardware based on Xilinx's Virtex®-7 2000T All Programmable

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At the European 3D TSV Summit in Grenoble, France on January 22-23, 2013, imec, a world-leading nano-electronics research institute, today announced that together with Cadence Design Systems they have developed,

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S2C's quad Virtex-7 2000T 3D IC rapid ASIC prototyping platform optimized for design partitioning. USA: S2C Inc. announced the addition of the newest prototyping platform, Quad V7, to its V7 TAI logic module series, a new

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January 19, 2013 - 8:33amFrancoise Von Trapp created the posting European 3D TSV Summit Sneak Preview

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[top] Overview | Registration [top] Overview The 3DIC Working Group begins 2013 exploring Business Models that will drive 3D IC market growth. These presentations tie directly to our 3D IC Business Models, 3D IC Roadmap

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Michael White takes a look at the current state of 3D IC chip packaging including 3D die-on-die stacking techniques and a variation called 2.5D die-on-silicon interposer packaging

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January 15, 2013 - 12:14pmFrancoise Von Trapp created the posting 2013 Predictions for 3D ICs as told by Everyone - Part 2

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Hi, What is the biggest obstacle in adoption of 3D IC technology. Is it 1. Lack of foundries and assembly houses which supports 3D IC Technology 2. Lack of EDA tools which is needed for 3D specific issues like thermal aware

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Development of TSV technology in China: a closer look. At the recent RTI 3D ASIP (Architectures for Semiconductor Integration and Packaging) conference in Redwood City Prof. Daquan Yu of the Chinese Academy of

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The presentation will also outline challenges of 2.5D and 3D implementation, highlight limitations with today's monolithic solutions, and offer alternatives for a high yield, integrated Die Level Handling environment

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3D Challenges in OSAT Nov. 6, 2012 ITPS in Hawaii Choon Lee Enabling a Microelectronic World® Supply Chain Model Amkor Proprietary Business Information 2 3D TSV Key Process Foundry / IDM / OSAT TSV Wafer

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January 9, 2013 - 9:03amDennis Dachtler... commented on TSVs Find Their Way into Prototypes saying This is really pretty much

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January 8, 2013 - 2:53pmFrancoise Von Trapp created the posting 2013 Predictions for 3D ICs as told by Everyone - Part 1

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The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC)

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business.wesrch.com - Papers - 3D IC Heterogeneous Integration, Business

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Heat removal from the stacked layers of 3D ICs has been an industry issue for many years, and has been thought to be a limiter on the types and performance of circuits that can be stacked. As well, hot spots in the stacked

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the 3D IC business initially, in the long term industry yields usually all level out, and then the sector will be driven by cost. IDMs will stay in the business as long as they see differentiation, but as the new technology matures,

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latency or parasitics, and the lower costs involved to produce effective 3D solutions for today's products. Face-to-face chip-on-chip technology. There are many ways to stack die: • Face-to-face IC assembly is the joining of two

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In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (for instance, stacking DRAM memory on CPU cores). A recent 3D IC report from

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MonolithIC 3D Inc., presented a paper at the IEEE International Electron Devices Meeting (IEDM) showing that effective cooling of 3D-ICs can be made possible by utilizing the circuits power delivery networks* (PDNs) and the

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Monolithic 3D-IC technology provides IC designers and manufacturers 10,000x higher vertical connectivity than state-of-the-art Through-Silicon Via (TSV) 3D technology. In addition to the 17 issued patents, the company has

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San Jose, CA (PRWEB) December 4, 2012 Monolithic 3D Inc., a startup in Silicon Valley, today announced it has been awarded its 20th patent monolithic 3D-IC

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[...]

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January 4, 2013 - 3:26pmFrancoise Von Trapp created the posting Tying up 2012 3D IC Loose Ends

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January 2, 2013 - 6:27pmStepha Gachp commented on Stress Management for 3D ICs using TSVs saying The argument that we are so

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January 2, 2013 - 4:51pmMichael Smith commented on The Transition to 450mm Wafers: What does it Mean for 3D ICs? saying I think that would be really

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SMD: What is ITRI doing in 3D TSVs? Lau: At ITRI we have developed the world's first Applied Materials' 300mm (3D TSV) integration line. The line was completed two years ago. We developed the process from the very

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USA: MonolithIC 3D Inc., presented a paper at the IEEE International Electron Devices Meeting (IEDM) showing that effective cooling of 3D-ICs can be made possible by utilizing the circuit's power delivery networks* (PDNs)

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We're going to see a big push to 3D-IC when Micron releases its 3D memory, too. Companies are going to look at it, realize its benefits, and buy it. This is going to offer a lot of improvement in system-level performance, and it's

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The theme of the first-ever Summit is “On the Road towards TSV Manufacturing,” a critical issue as device designers and manufacturers increasingly cross into the third dimension due to the industry's continuing pursuit of

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Mid-End: Fan Out, 3D ICS and 2.5D multi die interposers. The historical regularity of technological advancement, driving the expansion of functions on a chip at a lower cost per function and lower power per transistor has changed. The

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December 14, 2012 - 10:38amFrancoise Von Trapp created the posting 3D IC Pioneers Continue to Lead the Way

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December 7, 2012 - 5:12pmFrancoise Von Trapp created the posting Tips on Modeling Warpage for 3D ICs

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November 28, 2012 - 3:50pmFrancoise Von Trapp created the posting 3D TSVs: Will Europe Lead the Way?

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November 27, 2012 - 4:02pmFrancoise Von Trapp created the posting 2.5D and 3D FPGA Update

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November 21, 2012 - 3:53pmFrancoise Von Trapp created the posting 3D IC Blogosphere Update

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November 15, 2012 - 11:36amFrancoise Von Trapp commented on 3D ICs and the Hype Cycle saying Regarding #5 Jayna - Thanks

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November 15, 2012 - 11:15amPaul Werbaneth commented on 3D ICs and the Hype Cycle saying Hi Jayna, Thank you for the

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In 2012, 3D TSV is one of the hottest technologies, along with 450mm and EUV, in the semiconductor industry due to the technology's huge potential. Depending on the type of application and timeframe, gains in bandwidth,

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The next generation FPGAs, second generation SoCs and 3D ICs will be 'co-optimized' with Vivado for the most compelling alternative ever to ASICs and ASSPs. From enabling programmable logic, the Xilinx 20nm portfollio

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STATS ChipPAC a leading semiconductor test and advanced packaging service provider, announced that its Through Silicon Via (TSV) capabilities have achieved a new milestone with the qualification of its 300mm mid-end

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November 13, 2012 - 10:50pmIra Feldman commented on 3D ICs and the Hype Cycle saying Francoise, Many thank for

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November 5, 2012 - 1:55pmFrancoise Von Trapp created the posting Tezzaron, Novati and 3D ICs: They’re doing it in the USA

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According to IC Insights' 2012 McClean Report, “The assembly and packaging of ICs no longer takes a back seat to front-end processing…packages have evolved from simple cookie-cutter type packages to highly sophisticated and

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Global leaders in 3D technology will convene to discuss the latest advances in Grenoble on January 22-23, 2013 at the European 3D TSV Summit. This new SEMI event will take place in the heart of the French Alps, in one of

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While everyone’s waiting for the big memory houses like Micron and Samsung, and IDMS and foundries like IBM and TSMC to announce they are ramping to high volume manufacturing (HVM) with 3D ICs, deep in the heart of Texas, it’s already happening in low volumes for custom applications thanks to Tezzaron Semiconductor and its recent acquisition, Novati Technologies (formerly SVTC Technologies)

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Next month, SUSS MicroTec invites you to the Asia Technology Forum covering the latest in materials, manufacturing technologies and market trends in 3DIC and Wafer Level Packaging. The SUSS Asia Technology Forum

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electronics.wesrch.com - Papers - 3D IC Packaging Enablement Challenges Ahead - a panel of experts, High Tech

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October 23, 2012 - 3:10pmFrancoise Von Trapp created the posting 3D IC Educational Opportunities

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Please join us at Advantest on Oct 24th, at 1:30 PM (PDT), as we continue to explore pertinent topics impacting 3D IC product development, adoption, and production. Registration Click here to register for the meeting

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SemiMD sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Dr. Ahmed

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Network with Cadence technologists and peers in the Cadence Community. Stay abreast of technology trends, news and opinion through Blogs, forums, and social networking

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Network with Cadence technologists and peers in the Cadence Community. Stay abreast of technology trends, news and opinion through Blogs, forums, and social networking

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Last week I wrote that TSMC had validated Synopsys' design flow on its 3D-IC process. Today I received a press release from Cadence stating fundamentally the same thing with regard to its design flow. It is clear that work on

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Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that its full suite of 3D-IC technologies were deployed by Taiwan's Industrial Technology Research Institute

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Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that TSMC has validated Cadence® 3D-IC technology for its CoWoS™ (chip-on-wafer-on-substrate)

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May be you think the 3D-IC pace of development is too slow, but I am of the opposite point of view. Synopsys announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS™ (Chip

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Community. "Yes,3D IC is a compelling path for future scaling but not just the stacking version/TSV but far more so the monolithic 3D..." - Zvi Or-Bach. Comment from: Where Does It Hurt?

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A strong candidate is stacking memory NAND dies one on top of another. The dies are connected using Through Silicon Vias (TSV). Toshiba has a different approach to 3D " not stacking NAND chips one atop the other but

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October 11, 2012 - 12:14pmFrancoise Von Trapp created the posting This Week in 3D IC News (Oct 8-12)

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October 9, 2012 - 11:11amFrancoise Von Trapp created the posting SEMICON Europa 2012 Focuses on Materials, 3D ICs, and 450mm

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About this Entry. V2.5 ints, simulator 2D and 3D-IC-Open Source was was posted on October 4th, 2012 at 2.40pm and is filed under Meindl. This entry has no comments (yet). You can follow any responses through the RSS 2.0 Feed

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October 1, 2012 - 12:38pmFrancoise Von Trapp created the posting Talkers vs. Doers in the 3D IC World

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Intel is the number one semiconductor company in the world and has taken the lead in bringing FinFET (aka Tri-Gate) silicon to market at the 22nm node starting in May 2011, so now we see the pure play foundries playing catch-up and start talking about their own FinFET roadmaps. IC designers and layout engineers want to know how their design methodology will change as they consider using a FinFET process compared to a planar process

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PTI expect 3D IC technology to start generating income in 2014... Sep 21st. A*STAR's Institute of Microelectronics and Hitachi Chemical to develop 3D IC packaging ... Sep 20th. Silicon & glass interposers among the top 5 key

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3D ICs add a new dimension to design with new degrees of freedom possible, even with the added design and manufacturing complexities. Looking at the semiconductor ecosystem today and anticipating what will be needed

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Free Outline - Monolithic 3D Inc., the Next Generation 3D-IC Company - …, Outline - Monolithic 3D Inc., the Next Generation 3D-IC Company - … ppt, Outline - Monolithic 3D Inc., the Next Generation 3D-IC Company - …

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SPTS Technologies, the company that provides wafer processing solutions globally for semiconductor packaging, MEMS, power management device markets and such related markets, has introduced a low temperature

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September 19, 2012 - 11:27amFrancoise Von Trapp created the posting SPTS Debuts Low-Temperature PECVD Technology for 3D-IC

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Today GlobalFoundries announced a 14nm process that will be available for volume production in 2014. They are explicitly trying to match Intel's timeline for the introduction of 14nm. The process is called 14XM for eXtreme Mobility since it is especially focused on mobile. The process will be introduced just one year after 20nm, so an acceleration of about a year over the usual two year process node heartbeat

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future landscape of 2.5D / 3DIC chip-to-package manufacturing. The sea change of finally bringing 3D into mainstream production will mean major challenges and opportunities for the supply chain, as companies figure out where best to focus

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The adoption and commercialization of 3D TSV stacking IC technology and products will likely take place in the 2015-16 timeframe, according to Tong Ho-ming, general manager and chief of R&D at Advanced Semiconductor

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His topic: Using Repair & Redundancy with KGD to Produce Cost Effective 2.5 and 3D Devices. Of course, you don't build 2.5D or 3D IC assemblies without known good die, so this conference is a natural for anyone involved

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Industry migration to 3D ICs to take place in 2015-16. The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies

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MediaTek hikes smartphone chip shipments goal. MediaTek has revised upward its forecast for 2012 smartphone-chip shipments to 95 million units. 28nm chips in short supply at TSMC. Taiwan Semiconductor Manufacturing

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The OSAT player has extended its capabilities in mid-end and back-end TSV manufacturing to increased 2.5D and 3D packaging integration

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August 29, 2012 - 4:32pmFrancoise Von Trapp created the posting The Transition to 450mm Wafers: What does it Mean for 3D ICs?

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August 24, 2012 - 4:14pmFrancoise Von Trapp created the posting When 3D is 3D IC, and When it’s Not

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With the number of challenges 3D technology brings, will it complicate matters for the computational lithography tools that ensure printability? Fret not

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First 3D-IC Standard Approved! Formed in late 2010, the SEMI 3DS-IC Committee recently approved its first Standard for publication during SEMICON West 2012. Pending successful procedural review, the Document will be

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August 17, 2012 - 11:45amFrancoise von Trapp created the posting Wanted: Alternatives to TSVs

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August 8, 2012 - 3:35pmFrancoise von Trapp created the posting SEMI Standards, the ITRS Roadmap and other Boring but Important Items for the Progression of 3D IC manufacturing

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SEMI’s 3DS-IC Committee recently approved its first standard

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s (TSMC's) development of 3-dimension IC packaging for 20nm process technology it is working on, Taiwan's leading IC assemblers are vigorously boosting 3D IC packaging and test capacity. The assemblers include

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August 7, 2012 - 4:38pmFrancoise von Trapp created the posting Design and Test Solutions are Trending in 3D ICs

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Accelerate 3D-IC Integration for RF Applications: More than Moore - A Necessity for RF? Agilent Series Part 2 of 3. Moore's Law (the number of transistors on a chip doubles every 18 to 24 months) has driven microelectronics

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Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading →

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July 31, 2012 - 2:29pmQ3D Notes created the resource "The Demands and the Challenges of TSV Technology Application in IC & System

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Improved performance, reduced timing, reduced power consumption and device scaling attributes are key driving forces for the adoption of new microchip technology for mobile devices referred to as 3D integrated circuits

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SEMI Europe today announced that it is organizing a new event — the European 3D TSV Summit on January 22-23, 2013 in Grenoble, France. The theme of the first-ever Summit is “On the Road towards TSV Manufacturing,”

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If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)

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July 15, 2012 - 5:53amFrancoise von Trapp created the posting Outside the 3D TSV Box

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First of three parts: Planning for success in 3D ICs isn't so easy, particularly when power and thermal issues are factored in. Tools have been created, but are largely untested and may need modification

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The topic of the interview was cooling of 3D IC devices. It's no secret that cooling will become an issue when you stack a bunch of hot die together and bond them. The heat has to go somewhere and the heat from the middle

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Jul 19th, 2012. Nanya demonstrated its 1st functional 3D stacked DDR3 SDRAM using TSV middle. Nanya Technology Corporation successfully demonstrated its first functional TSV (Through Silicon Via) 8Gbit DDR3 SDRAM QDP (Quad-Die

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Advantest Corporation today announced that a new product line of fully automated and integrated test and handling solutions for TSV based 2.5D and 3D products is under development. Send to a friend. The concept model

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ADVANCED PACKAGING. Jul 17th, 2012. A giant leap? An evolutionary path? How all roads lead to 3D. Here is an interesting article discussing 3D packaging adoption, especially for NAND flash memory. Send to a friend. With Intel already

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In March of this year, Altera announced "the world's first heterogeneous 3D IC test vehicle using TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process". TSMC is planning to offer the CoWoS process as part of a

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ARM and TSMC are teaming up to optimize next-generation 64-bit ARM cores for FinFET process technology. And that must be leaving Intel feeling rather smug. After all, it completely validates what the chip behemoth said at its investor day -- in both Paul Otellini's and Brian Krzanich's presentations – that Intel is a good four years ahead of its closest foundry competition

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There has been a lot of talk recently about 3D ICs and the challenges associated with them. One area that contains some of the biggest challenges is related to power – how do you get power in and how do you get the heat generated back out again. To understand this a little more, I talked to Madhavan Swaminathan who is the Joseph M. Pettit Professor in Electronics at the School of Electrical and Computer Engineering and Director of the Interconnect and Packaging Center (IPC), an SRC Center of Excellence, at Georgia Tech, Atlanta. He is also the Founder and CTO of E-System Design

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This is a wrapup of the 2012 Design Automation Conference (DAC 49) with emphasis on some of the trends that were evident at the event

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Michael White takes a look at the current state of 3D IC chip packaging including 3D die-on-die stacking techniques and a variation called 2.5D die-on-silicon interposer packaging

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The most common form of 3d technology involves through silicon vias, but a startup company called Monolithic 3d has an alternate approach. In an interview with Sander Olson for Next Big Future, Monolithic CEO Zvi Or-Bach

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Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors

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Yes, unless we Augment Dimensional Scaling with monolithic 3D-IC Scaling [...]

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[...]

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Silicon interposers competed with TSV at ECTC. Gazing over the scenic San Diego harbor, more than a thousand people gathered at the Electronic Components and Technology Conference (ECTC) to discuss cutting-edge developments in electronics packaging, materials, and assembly.

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At the tail end of last year Sony released their PlayStation Vita, and it was duly torn down by iFixit and others. In due course we took it apart too, though we didn’t post it on our teardown blog. Sony CXD5315GG in the PlaySation Vita Inside we found the usual set of wireless chips, motion sensors, and memory, but the key to the increased performance of the PS Vita is the Sony CXD5315GG processor, a quad- core ARM Cortex-A9 device with an embedded Imagination SGX543MP4+ quad-core GPU

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A bunch more IT vendors have picked up shiny new Hybrid Memory Cube sledgehammers and are working with Micron Technology and Samsung Electronics to smash the memory barrier

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The impact of via-middle Cu TSVs on neighboring devices and overlying low-k interconnect has long been a key concern for integrating TSVs into deep submicron CMOS. The TI researchers used NanoBeam Diffraction (NBD)

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I first covered the Hybrid Memory Cube in the EDA360 Insider nearly a year ago. (See “3D Thursday: Micron's 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs”

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I listened in on yesterday’s webcast, 3D and 2.5D Integration: A Status Report Live Event hosted by Solid State Technology, and while most of the information was similar to what I had heard at IMAPS Device Packaging Conference, EDPS, ECTC 2012, etc., they are clearly messages worth repeating, and some new interesting nuggets as well

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Note to self: no more graduations/college orientations/vacations in the month of June. There are way too many events in 3D and I missed so much while I was off focusing on other things! Lucky for me, people writing and blogging about 3D technologies are coming out of the woodwork, and so as I catch up on my reading, I’ll point you to some of the key points made by my capable colleagues in the 3D blogosphere

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Note to self: no more graduations/college orientations/vacations in the month of June. There are way too many events in 3D and I missed so much while I was off focusing on other things! Lucky for me, people writing and blogging about 3D technologies are coming out of the woodwork, and so as I catch up on my reading, I’ll point you to some of the key points made by my capable colleagues in the 3D blogosphere

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It's a little known fact that these 3D IC assemblies have been in volume production for a while and are widely used in the low-cost imagers used, for example, in mobile phone handsets and tablets. Target total capacity is

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Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading →

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At the TSMC Theater Apache (don't forget, now a subsidary of Ansys) talked about Emerging Challenges for Power, Signal and Reliability Verification on 3D-IC and Silicon Interposer Designs. The more I see about the costs and challenges of 20/22nm and below, the more I think that these 3D and 2.5D approaches are going to be one of the main ways that we keep on the Moore's law curve at the system level

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3D has been a growing buzz word in IC design and packaging for several years now, so it's refreshing to actually find an EDA vendor that has developed tools to help analyze something like 3D thermal and mechanical stress at DAC. I met with Jens Andersen, CEO of Invarian to learn more, although my only mistake was that every few minutes a colleague or prospect would stop by and say hello to Jens and interrupt us. The Invarian booth had visible traffic that kept the staff engaged

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PTI's R&D efforts in 3D IC and other advanced packaging processes will start to bear fruit in 2013, said Tsai, adding that the complete offering of new technologies provides the firm a better chance of being the fourth-largest IC

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I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his

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Since the discussion covered both 2.5D-IC and 3D-IC technologies, here's some quick background. In general, 2.5D refers to multiple silicon dies placed side-by-side on a silicon interposer substrate. A "true" 3D-IC stack

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Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about Reiter before but I’ve just found out at lunch that he’s been crowned as the “King of 3D ICs” by Françoise von Trapp, Editorial Director of 3D-ICs.com and the Queen of 3D (as proclaimed at SEMICON Europa 2007), because of the four years Reiter has put into learning about, cheering on, and supporting the growth of 3D IC assembly. (I am pretty certain that Reiter is glad he’s not been named the Queen of 3D.)

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So here I am in Honolulu with my family, celebrating the return of my nephew from a 6 month deployment on a nuclear submarine, and I realize that the co-located IEEE Symposia on VLSI Technology and IEEE Symposia on VLSI Circuits is taking place at the SAME TIME, and there's a couple of sessions on 3D technologies!! So rather than joining my gang on a scuba diving adventure, I send them off to explore the ocean depths and take myself over to the Hilton Hawaiian Village to check out the 3D action. (Ok, this isn't exactly how it happened, but it makes for a good story, and most of it is true.)

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Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx's 3D Virtex design because it is about the only one that is in manufacturing (it is so high end I hesitate to say it is "volume manufacturing")

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Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds

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Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate (CoWoS) process, TSMC has taken a step towards

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Video Blog: At ECTC 2012, 2.5D and 3D technologies were the main topic of conversation, both in formal panels and off-line discussions. 3D InCites talked to a number of industry experts to get their perspective on the status of 3D as we move closer to commercialization

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The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic

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The Global Semiconductor Alliance (GSA) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA

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With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together

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3D-IC represents different benefits for different applications. It can be both a performance enhancer and a power reducer due to shorter, lower capacitance interconnect lines, for example when used to stack memory on logic. It can provide a smaller overall footprint for mobile apps like cell phones, and it can improve yield when multiple smaller die can be assembled in lieu of a large SoC during early process maturity. It also allows analog and digital IP to hit performance and integration targets without forcing implementation in a single process. Depending on the application targeted, the jury is still out about relative costs and reliability, but there expectations for improvement in the long run in these areas as well.

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Wow, times have changed. Who would have thought the foundries would ever willingly turn to the packaging industry for the solutions to future scaling? But I heard it myself yesterday at the ECTC luncheon keynote address, straight from the lips of Global Foundries’ CTO Greg Bartlett, who said that “silicon is not a great place to be right now,” referring to challenges with scaling beyond 28nm, and how scaling is running out of steam. “We’re looking across the abyss to packaging and hope 2.5D and 3D guys are going to throw us a life preserver.” That statement, I’m pretty sure, was music to many more ears than just mine – and particularly those who have been driving the move to 3D integration for the past several years

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ECTC sure knew how to pack ‘em in early this year! It was no accident that they held a special session on the Transforming Role of the Packaging Foundry on the Professional Development Course Day (Tuesday, May 29). Instead of 30 or so stragglers who wandered in between their regular courses during last year’s special session, there was standing room only at this session (I’m told 150+ people) and it was easy to understand why: how often do you get all the major OSATS represented on one panel?

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Cadence's Richard Goering interviews one of his colleagues, Ken Potts, about the GSA's 3D IC working group. For an ecosystem to build technology this complex, we're going to need lots of standards groups like this one

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We’ve all heard it: Wide I/O DRAM on Logic using TSV interconnects will be THE solution for achieving the high performance/low power needs of next generation devices, beginning with the high performance computing and making its way into gaming processors, smartphones and tablets. To listen to the experts, meeting such performance goals as true HD, faster video streaming, multi-cameras, multi-application operation, and other processor-intense applications that require higher bandwidth at slower clock speeds can only be done with Wide I/O (Figure 1). Unfortunately, it looks like manufacturing logistics will push out the previously scheduled forecasted timeframe for Wide I/O DRAM on Logic package configurations from 2014 to as late as 2016. So what are we to do in the meantime?

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The Global Semiconductor Alliance (GSA) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers, and other important ecosystem players can come together and work through the business and technical challenges posed by 3D-IC technology. Ken Potts, product marketing director at Cadence, recently became the chairman of the GSA 3D IC Working Group. In this interview he talks about the business and technical challenges facing 3D-ICs, the role of the GSA working group, the advantages of 3D-ICs, the need for standards, and when 2.5D and 3D-ICs will come into volume production

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Scalability (in terms of capacity, performance, and functionality), because no one can see five years ahead; More bandwidth; New packages (to accommodate 3D IC assembly and thermal issues); Lower power consumption

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In the May 15 issue of Future Fab News!, Aaron Hand, contributing editor, asked for opinions on Mark Bohr’s (Intel) now famous EE Times interview, with Rick Merritt, where he said the fabless model is collapsing and a return to the IDM is inevitable. (I addressed a similar topic a year ago in a post titled Will 3D Integration Keep 2nd Tier Foundries Alive?) So for what it’s worth, here’s my input, from the perspective of the 3D IC industry, where things are progressing quite nicely, thank you, and the fabless/foundry/OSAT model seems to be the most desired for a multitude of reasons

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Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die.

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So with all of those benefits, is IBM looking into 3D IC assembly? If you've been reading the EDA360 Insider blog, you know the answer's “yes.” (See “3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway to

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While I was marlin fishing in Hawaii last week I missed some interesting comments from TSMC executives at the Technology Symposium in Taiwan, a much different show than the one here in San Jose I’m told. It is good to see TSMC setting the record straight and taking a little credit for what they have accomplished! I’m sorry I missed it but I know quite a few people who didn’t and they were quite impressed

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Want to know how to torture a journalist? Invite them to present at a conference but ask them to sign an NDA so they can’t write about it! However, I can say this much: the 3D Program is alive and well at IBM. From IBM Fellow, Subramanian Iyer, I learned some basic truths about scaling and 3D. One of the current challenges being faced where 3D can provide the solution is in the power budget. Communication between chips can take up to a third of the system power. “Semiconductor scaling doesn’t address this issue, but tighter inter-chip connections can,” notes Iyer. “3D does not eliminate the need to scale, it’s an orthogonal element for increasing performance.” He added that the cost per transistor still needs to come down

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Visit any major city on the planet, roll through its development over the past 100 years and you’ll notice something about the height of the skyline. When you need to pack more people into a fixed area, X and Y are not enough. You MUST build upwards. KitGuru casts an eye over Microsoft’s need for a better packing density

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The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including

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And because of the development of Smartphones which can do more and more things the development will go to higher integration between both volatile and non-volatile memory in 3D IC beneath SoC processors fortcoming

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“I’ve been a big fan of Phil’s ever since his first blog in August of 2007. Did you know he was born in Hell’s Kitchen in New York City? Congratulations to the world’s foremost expert on 3D integration on his 100th blog!” -- Peter Singer, Editor-in-Chief, Solid State TechnologyIMAPS France held the 2nd Micro/Nano-Electronics Packaging, Assembly, Design and Manufacturing Forum (MiNaPAD) in Grenoble in late April.

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What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won't have to? That's the topic of the upcoming DAC panel: “Is 3-D Ready for the Next

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If you're like me, you've heard more than enough theory about 3D IC assembly and you're ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will

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ulti-die configurations and a switch to copper wires are rampant, and supercomputers are why. One of the main topics at conferences around the world is what’s the driver for electronics packaging for the next 10 years? The Joint Conference of the 12th International Conference on Electronics Packaging and IMAPS ALL Asia Conference that convened in Tokyo in late April was no exception

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The release of Redhawk-3DX, by Ansys subsidiary Apache Design Inc., demonstrates the increasing attention that EDA vendors are giving to tools for stacked-die packaging in the last several months. Just one year ago, the

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Really, it all boils down to simple economics. I’m referring to WHY the road to 3D is taking as long as it is to reach commercialization. We’ve convinced the engineers of the technology benefits. Now it’s time to convince those who hold the purse strings: the management

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I don’t get to attend all the 3D events that I would like to, and such was the case with this year’s GSA Silicon Summit, held Thursday, April 26, in San Jose. But I did get some insight from Rich Rice, Senior VP of Sales and Engineering, ASE, who was a panelist on the afternoon 3D Packaged IC Ecosystem panel discussion, and whom has also participated in a number of similar panel discussions over the past year

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At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position would need to be taken by someone funded by the company they work for. So thanks Cadence. And thanks for the beer and wine after the meeting too

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Qualcomm has been working on 3D IC technology development projects to help prepare the company for a 3D future. “3D DRAM stacking has started—it's shipping in products because it has maintained the bit density/cost

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3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York. Posted on April 26, 2012 by sleibson2. Customers' clamor for 3D IC assembly capability and die with TSVs

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Drawing the analogy of the human brain, the company's niche buffer memory products act like the memory, its USB3.0 host products are like nerves that provide connectivity, and the webcam IC provides vision just like our eyes. The flash drive – commonly known as a thumb drive – is now moving from USB2.0 into the USB3.0 era. Etron's recently launched USB3.0 device control ICs break new world records in terms of speed, adding a "thumbs up" to the coming of the information age of convenient, connected and portable 3C electronics

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Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques

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The IC industry must embrace — and become more active — in the standards process to help jumpstart the 2.5D/3D chip era, according to a panel at the recent Mentor Graphics User Group Meeting in Santa Clara, Calif

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In the panel session at EDPS on 3D IC a number of major issues got highlighted (highlit?)

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D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. In the last few months it has been described in detail at the IEEE ISSCC and the DAT- Europe conferences. I-Micronews thought it was worth “A Close Look”.

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Funny thing is, as moderator I was not able to take any notes during the panel and that was most unfortunate because the panelists covered a lot of interesting ground with respect to 3D IC design and assembly issues

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In addition to my Monday blog post, there has been a plethora of articles authored by other industry bloggers about the 3D Friday event, most of them focused on the user perspective, as well as the panel. I haven’t seen a whole lot of attention paid to the vendors, Mentor, Cadence and Synopsys – all who had some input on their company’s offerings and readiness for 3D IC so far. So I will give them some air-time here

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In the past IFTLE has ranted about how every technical conference on the face of the planet wanting a piece of the 3D integration pie and how that is propagating severe redundancy in the presentations that are being given. Paying $500 + travel expenses for a conference that gives you 15 3D presentations when you have already seen 12 of them under slightly modified titles can be upsetting. Going to a conference that gives you 1 session of 3DIC presentations and you’ve seen all 5 of them is even worse. I don’t blame the presenters, because I know they are being begged by the session chairs to submit their presentations even if they admit that they have nothing new to say.

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The second day (more like a half-day) of EDPS was devoted to 3D ICs. There was a lot of information, too much to summarize in a few hundred words. The keynote was by Riko Radojcic of Qualcomm, who has been a sort of one-man-band attempting to drive the EDA and manufacturing industries towards 3D. Of course it helps if you don't just have a sharp arrow but the wood of Qualcomm behind it. Curiously, though, Qualcomm themselves have been cautious in actually using 3D IC technology. Possibly they have done some test chips but I don't know of any parts that they have in production. Other presentations were by Altera, Mentor and Cadence, plus a panel discussion

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It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of 3D-IC experts at the recent Electronic Design Processes Symposium (EDPS) April 6, 2012 in Monterey, California

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Last week's Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you'll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published

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It's April 2012, and both spring and 3D-ICs are in the air. But if Spring means April showers and May flowers, what do 3D-ICs mean? Well, if you were at EDPS in Seaside this morning, at the Monterey …

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While it was Good Friday for most, it was 3D Friday for those of us who attended the 19th Annual Electronic Design Process Symposium (EDPS), held last week in Monterey CA. What an amazing location! For an ocean-starved desert dweller like me, it was hard to tear my eyes off the waves and pay attention at what was going on in the front of the room... but I managed and it was definitely worth tuning in to

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FPGA is a product designer can modify their internal logic advantage.TPA5052RSAT Suppliers. As the development of the continuous rise in the cost of ASIC and ASSP alternatives, more and more electronic products start with FPGA. FPGA competitiveness from the source in the semiconductor manufacturing technology of micronized. FPGA is maintained in the same design under the premise of increase production, very suitable for mass production, can make the enterprise for the first time using the most sophisticated manufacturing technology. Therefore, FPGA to ASIC, ASSP have obvious advantages, promote the formation of the enterprise by using the benign loop

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You will need to travel to Milan, Italy to attend the 4-day intensive event devoted to non-volatile memory, which seems to be the exclusive topic for the 4th International Memory Workshop Symposia on VLSI Technology and Circuits covers latest STT-MRAM developments being held on May 20-24.

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Lots of changes are ahead, but at least no one is glossing over what needs to be done anymore

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On the power side of 2.5D designs there are some extra issues that have to be considered during the design process, pointed out Steve Smith, senior director of 3D IC strategy and marketing at Synopsys. “For example, the die

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ASTRON, the Netherlands Institute for Radio Astronomy and IBM announced an initial 32 million EURO, five-year collaboration to research extremely fast, but low-power exascale computer systems targeted for the international Square Kilometre Array (SKA)

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A few weeks ago in Dresden “Design, Automation and Test” held its annual European conference better known as DATE. ARM, IMEC and the Swiss Federal Institute of Technology (EPFL) gave an interesting presentation on the “Performance and Efficiency of 3D Stacked DRAM in a Multicore System”. iMicronews thought it worthy of “A Closer Look”

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Seems like yesterday that the packaging world was hearing that Fujitsu, Toshiba, NEC, Oki, Renesas and others had formed a pre-competative consortium under the Association of Super Advanced Electronics Technologies to study direct connecting of chips with through silicon vias (TSV). It seems like yesterday but it was 1999, 13 years ago.

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One of 60 research institutes that make up Germany’s Fraunhofer Gesellschaft, the Fraunhofer Institute for Reliability and Microintegration IZM is known worldwide for its work in the realm of microelectronic packaging and system integration. The center ASSID (which stands for All Silicon System Integration Dresden) was established as a division of Fraunhofer IZM with the core mission of developing 3D integration, interconnection and assembly technologies for the heterogeneous integration of multi-functional electronic devices into one wafer-level system-in-package (SiP). Its state-of-the art cleanroom facility houses a complete leading edge 300mm process line for through silicon via (TSV) formation, TSV post processing on the wafer front and backside, pre-assembly, 3D device stacking assembly, as well as test and in-line methodology for process control. I had the opportunity recently to visit the center in Dresden, Germany and meet with M. Juergen Wolf, who, besides being strongly engaged in Fraunhofer IZM’s wafer level system integration activities, manages and coordinates IZM-ASSID. Wolf shared some details about what distinguishes Fraunhofer IZM-ASSID from other 3D integration research programs at Fraunhofer

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OSATs are facing off with foundries over next-gen packages. Two poker games occurred at the IMAPS Global Business Council and International Device Packaging Conference held in Ft. McDowell, AZ, in early March. One was a game of Texas Hold’em for attendees; the other had much bigger stakes.

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Micron will be presenting the morning of Friday, April 6 during what I've been calling 3D Friday. You now have less than a week to sign up for this event and if you have any interest in 3D IC assembly, then you need to be in

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Two years ago, I visited EV Group’s world headquarters in Schärding, Austria, and wrote about what they call their Triple I approach to success. Triple I stands for Invent, Innovate, Implement, and refers to EVG’s mission of getting into whatever market they target at the ground level, investing 20% of its revenue in R&D, and working alongside customers to bring new technologies to market. “I’m fully convinced that Triple I is the engine for our growth by being in the forefront of innovation. One of our strengths and engines for success is our huge investment in product support and product development, which gives us a clear advantage to providing the right capabilities and establishes the groundwork for future growth,” notes Hermann Waltl, executive sales & customer support director, EV Group.

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This week at Design West (the conference previously known as the Embedded Systems Conference), I had a chance to speak with Mike Black from Micron about the Hybrid Memory Cube (HMC), a 3D DRAM assembly aimed at high-performance computing. The first thing he told me was that Micron had built an operational prototype of the HMC. It delivers 121Gbytes/sec of bandwidth, about 95% of the target bandwidth: 128Gbytes/sec. He promised to send me a photo, but it looks like a prototype not a finished product so Micron has not been eager to pass the image around

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Synopsys announced a 3D-IC initiative to accelerate the design of stacked multiple-die silicon systems. The initiative will use 3D-IC integration

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Because this slide clearly shows an intersection between 3D IC assembly and analog chip technology—something usually not overly discussed in 3D IC technology coverage—I took the opportunity to interview Dr. Menon

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Synopsys 3D-IC EDA Solution. DFTMAX Test Automation Design-for-test for stacked die and TSV; DesignWare STAR Memory System IP Integrated memory test, diagnostic and repair solution; IC Compiler Place-and-route

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Eeek alors! The net is buzzing with the news that the folks from Altera and TSMC have just announced their joint development of what they describe as “The world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process” (see also Dylan McGrath’s column TSMC, Altera team on 3-D IC test vehicle)

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And no red and green glasses required. I remember the first time I heard about a Through Silicon Via (TSV), punching a hole through the entire wafer to make an electrical connection at the back, like we do all the time in printed circuit boards with through plated holes. I thought someone was trying one on and trying to make me look a fool. But it is real and becoming realer (as my daughter used to say)

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In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory controller, GPU, IP block and peripheral units is very difficult to test as a whole system together

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3D InCites just published a short piece on glass interposers for 3D ICs, as discussed at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ. If you're interested in seeing a more

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3D-IC has vias in silicon containing active circuitry. 2.5D is similar, but uses ... While both 3D-IC and 2.5D technologies reduce PCB real estate, 3D-IC has the promise of having a greater real estate reduction. There is also the

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Because this slide clearly shows an intersection between 3D IC assembly and analog chip technology—something usually not overly discussed in 3D IC technology coverage—I took the opportunity to interview Dr. Menon

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In the explosive growth of multifunction mobile devices, such as smartphones and tablets, it has become essential to produce thinner and smaller low power consumption devices with increased functionality. Advanced packaging technology addresses this need and, in particular, wafer level packaging to form Lead-free / Cu- pillar bumping and TSV (Through-Silicon Via) on the silicon wafer has emerged as the fastest growing semiconductor packaging technology for over the next 5years to come

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3D InCites talks to conference attendees and participants to find out about the progress of 2.5D and 3D IC Packaging technologies. Thanks to Keith Cooper, SET NA, Jerome Baron, Yole Developpment, Kathy Cook, Ziptronix, Ron Huemoeller, Amkor, and Kim Pollard, Dynaloy, for your participation. Oh - and thanks to the guy at the very end who says, Come on, Really?

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1st day: Misha Buric, CTO of Altera, talking about SoC FPGAs and other things; Dinner: Jim Hogan, himself, talking about SoC Realization; 2nd day: Riko Radojcic, director of engineering at Qualcomm, talking about 3D IC

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I've written previously about the all-3D IC design, assembly, and packaging program that will take place during the second day of the EDPS (Electronic Design Process Symposium) workshop in Monterey. This blog post is to

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At the recent IMAPS Device Packaging Conference in Ft McDowell AZ Nick Kim , VP of electronic packaging technologies at Hynix, addressed upcoming packaging challenges.

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What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium

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For those of us who attended Doug Yu’s keynote address at the 3D Architectures for Semiconductor Integration and Packaging Conference in December, yesterday’s keynote at IMAPS DPC was, in the words of the immortal George Carlin, “déjà vu all over again”; driving home the message that yes, TSMC intends to provide full 2.5F and 3D service including chip design and fabrication, stacking and packaging. While he didn’t actually state TSMC’s intentions formally in his address titled “System Scaling Superhighway”, Yu, who is senior director of integrated interconnect and packaging, R&D at TSMC, outlined the key technologies that offer the best path to commercializing 3D integration technologies, with the implication that TSMC is well positioned to provide them all

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Here’s something new from previous Device Packaging Conferences – rather than a panel largely populated by members of the EMC3D Consortium (ie: suppliers) moderated by either Jan Vardaman or Phil Garrou, the panel was populated by foundry and OSAT representatives, a fabless company, a market analyst, and still moderated by Phil Garrou. Specifically, the panelists included Doug Yu TSMC; Jon Greenwood, Global Foundries; Remy Yu, UMC; Nick Kim, Hynix, Ron Huemoeller, Amkor; Rich Rice, ASE; Matt Nowak, Qualcomm; and Jan Vardaman, TechSearch International. This alone was a clear indicator that indeed, 3D has moved beyond what has become known as ‘powerpoint engineering’ and is headed full tilt toward commercialization

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Its going to be a busy 3D week here at IMAPS Device Packaging Conference, in Scottsdale AZ. So I’m going to attempt to keep up with everything with short, daily blog posts. I can’t promise to cover everything in detail (hey, if you wanted that, you should have come yourself!) As I’ve said in the past, if you attend a number of conferences each year on a topic, you tend to hear a lot of repeat information. And with the snail’s pace of new technology adoption in the industry – it gets awfully redundant to keep writing the same thing over and over, so I’m going to try and spare 3D InCites readers from that and assume you all know the basics (market drivers, remaining technology challenges, need for standards, etc) and instead try to deliver what strikes me as new information. Let’s see how this goes

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I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago.

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For the first question, the panel (and EDAC members) were asked when 3D IC packaging, whether stacked die or "2.5D", where several silicon die are interconnected on an interposer, would become mainstream. This emerging technology is

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More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy. Posted on March 2, 2012 by sleibson2. Semiconductor memory analyst and expert Jim Handy has just published an overview of

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If you're not familiar with the RaspBerry Pi board, it's a very capable, Linux-programmable single-board computer with a package-on-package 3D IC assembly consisting of a 700MHz Broadcom ARM 11-based application

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Continuing to examine presentations from the 3rd Int IEEE 3DIC Conf held in Japan in Feb 2012.

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It wasn’t on the final agenda, but thanks to a last-minute presentation switch by BiTS Workshop keynoter Jim Feldhan, president of Phoenix-based Semico Research, 3D became a featured topic at this year’s event. For the past few years, BiTS General Chair, Fred Taber, has contracted me to conduct video interviews at the event for the BiTS Workshop website. The fact that I had the opportunity to get another analyst’s perspective on 3D was a bonus

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knew when I visited EV Group’s world headquarters in Schärding, Austria two years ago that there was an ongoing story here and I would be returning to write about the next phase of growth. (This time, we’ll be catching it all on video as well.) What I didn’t anticipate was the warm welcome we received at the Hotel Gugerbauer. As a returning guest, I was greeted as an old friend, handed a key and that was it. No registering, no showing of my passport. “You’ve been here before,” was the explanation. The room was lovely, the food - delicious; the sauna - reviving. It was a good way to rest up from the arduous journey from Dresden that involved navigating the autobahn in the rain and dark and rescuing our luggage from taking an unaccompanied side trip to Phuket

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3D-IC offers the promise of considerable miniaturization. The stacking of die that would otherwise be adjacent to each other reduces the area required on a PCB. While both 3D-IC and 2.5D technologies reduce PCB real

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I usually never miss the Academy Awards, but this year I am in Germany visiting Fraunhofer IZM ASSID in Dresden for a 3D InCites sponsored site visit, and decided against getting up at 2am to see first hand who won Best Picture. I was invited by M. Juergen Wolf, who manages and coordinates IZM-ASSID (which stands for all silicon system integration Dresden), to come and see what Fraunhofer’s program is all about. Unlike other site visits, this time I brought along 3D InCites staff videographer, Steve Rayle, to see if we couldn’t make an Oscar winner of our own

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A recent report by IMEC at the IEEE 3DIC in Japan focused on the Si stresses in 3D stacked ICs caused by the thermo-mechanical interaction of the underfill, microbumps and Silicon die.

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Backgrinding, which is used in nearly all 3D wafer thinning processes, is known to generate residual stress in the silicon and a layer of damage (crystalline defects and microcracks). Additional processes such as CMP, dry etch etc. are carried out after backgrinding to release the residual stress and minimize the damage layer

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The IC industry is revving up efforts to make 2.5-D and eventually 3-D IC technology a mainstream reality. The vision of a 3-D IC is promising, but some industry watchers believe the 2.5-D market to be more than a steppingstone to true 3-D design. They say 2.5-D technology has staying power. Leveraging it industrywide will require evolutionary, rather than revolutionary, adjustments to current design flows and the supply chain.

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The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512-bit data interface, JESD229 Wide I/O Single Data ­Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.

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A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains

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I've written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet Technology

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At the recent IEEE 3DIC meeting in Japan researchers from Nanyang University in Singapore reported on the 3D integration of MEMS and CMOS using Cu-Cu bonding to simultaneously achieve electrical and mechanical

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3D integration using through silicon via (TSV) has first been used for MEMS and CMOS image sensor integration: now 3D is moving to the mainstream IC business, with the emergence of wide input/output interface, stacked

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The growth of 3D IC and TSV has spawned a whole ecosystem for TSV technologies from industry, academia and research institutions, to equipment and material suppliers. The Secondary Equipment Applications, Service

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When process nodes reached 28 nm and below, it appeared that design density is reaching a saturation point, hitting the limits of Moore’s law. I was of the opinion that the future of microelectronic physical design was limited to 20 and 14 nm being addressed by technological advances such as FinFETs, double patterning, HKMG (High-k Metal Gate) etc... Probably, this limitation pushed the industry to look at other avenues such as growing vertically giving rise to 3D-IC, also enabling SoC arena, which is of interest today

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I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet Technology Summit. The speaker was Chris Bergey, VP of Marketing at Luxtera, and the topic was 100Gbps Ethernet (100GbE). This realm of 40GbE and 100GbE is presently the domain of optical interconnect, used primarily in data centers. Optical interconnect burns a lot of power, on the order of 20W/channel, so there’s a lot of interest in reducing the power consumption of these Ethernet connections because data centers tend to use a lot of them and the electricity needed to cool these systems is a substantial fraction of the data center’s operating cost

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I attended the annual IMAPS local chapter lunch here in Arizona last week and got the low-down on the semiconductor market and forecast from Bill McClean at IC Insights. Bill does a great job at showing the whole picture – comparing the Worldwide GDP and showing the correlation between it and the worldwide semiconductor market. He’s also good at relating theory to statistics, which helps someone like me, who always needs to know WHY, understand the charts and graphs. So rather than recite the percentages and charts here (hey, to get that you can just read the presentation here.) I’ll relay the major takeaways

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Guest Blogger John H. Lau, ITRI, Taiwan, poses an interesting question in this blog post. Please login and share your knowledge in the comment area provided

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3D packaging integration continues to increase in complexity, and as a result, it is driving more samples into FA labs for development support and failure analysis.

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The Electronic Design Process Symposium soon to be held in Monterey, California, will devote all of Friday, April 6 to 3D IC issues.

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It's not news that Apple has been considering moving fabrication of its A6 ARM processor from its current supplier Samsung to TSMC. The "A6," was scheduled to appear in the iPad 3 later in 2012

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I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?”) Now, Eric Beyne, Director of Advanced Packaging and Interconnect Research at Imec has published an article with key lessons learned from related work associated with stacking a special 3D logic die with TSVs (through silicon vias) and microbumps on a DRAM die and it’s a worthwhile read

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At a recent event, Ivo Bolsens, senior vice president and chief technology officer at Xilinx Inc., warned that the IC industry faces many challenges to make the giant leap into the 2.5D/3D chip era. Design issues, technical hurdles and supply chain complexities are among the challenges, Bolsens said. “The industry still has a lot of work to do,” he said at a recent 3D conference in Burlingame, Calif

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Although specific market forecasts differ -- some positive and some negative -- there seems to be overall agreement that 2012 will get off to a relatively slow start for the semiconductor industry. However, ultra thin high-performance laptops are a potential positive variable in the equation

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Last week, CEA-Leti launched its Open 3D initiative to the 3D world in an effort to make its mature 3D technologies accessible to industrial and academic partners for their advanced products and research projects. Wanting to learn more about this offer than was detailed in the press release, I interviewed Leti’s David Henry, Open 3D project manager. He not only provided answers to my questions, he also addressed those of M.P. Divakar, a 3D InCites member who posted questions on the press release post itself. (See how this interactive community thing works when people use it?)

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I am a conference junkie. I go to many 3D Integration conferences and would like to share one very important observation with you! Every time I look around me and check out the companies of the attendees, more than 95% are from:

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Three-dimensional (3D) integration is considered a very promising technology for integrated circuit design. It provides numerous opportunities to designers looking for more cost-effective system chip solutions.

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At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm, R3Logic, ST and TI.

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This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of Wide I/O SDRAM. The JEDEC Wide I/O SDRAM spec (JESD229) calls for a 512-bit-wide data interface (split into four independent 128-bit channels) running at 266MHz with one transfer per clock cycle (single data rate signaling). This spec was created specifically for the low-power needs of mobile applications such as mobile phone handsets, where the total amount of energy available from a charged battery drives nearly all design decisions. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”)

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he ASIC business is getting more and more complicated. The ability to produce innovative die at a competitive price to solve increasingly complex problems just isn’t enough. The technology required to package that die is now front and center.

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Nimbic, the leading provider of Maxwell-accurate, 3D Full-Wave Electromagnetic Integrity solutions, today announced that Jim Hogan, Nimbic Board of Director, will join the panel discussion titled “Why Do We Need 3D Design Standards?” to be held at DesignCon 2012 in Santa Clara, California

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Gabe Moretti is a long-time EDA analyst and commentator. His latest “Assembling the Future” newsletter highlights and summarizes key economic, architectural, and test issues associated with 3D IC assembly. Gabe writes:

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Looking at the huge gap between the revenue of semiconductor design and manufacturing (~$300B) and that of EDA tools, services and silicon IP combined (~6B) inspired me to look more deeply into the overall arena of semiconductors in today’s context and possibly decipher some trends which should emerge in near future. Although this gap in revenue always existed, in the realm of SoCs and ever increasing complexity on a single wafer over last few years, the gap seems to be justified and may open up new chapters in the semiconductor arena. I have been watching the developments in this space for a few years and the industry seems to be at an inflexion point. This prompted me to write this article

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One of the best received presentations of the conference was "A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC - a Practical Design Perspective" by Pascal Vivet, and Vincent Guérin. Going well past their allotted time during the scheduled presentation, they were brought back (by yours truly) after the session ended to answer questions for a further 45 minutes. While some of the presentation was beyond the capability of the management and process development audience, the importance of the contribution was crystal clear to everyone

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Last week, SEMATECH and ISMI announced they would be conducting Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high volume manufacturing (HVM) maturity issues for 3D IC manufacturing. This is a significant step in SEMATECH’s goal to accelerate the 3D technology revolution. To find out more about this, I talked with Sitaram Arkalgud, director of the 3D program at SEMATECH, and Lorn Christal, project manager at ISMI, about the EMA process, and how this focused assessment of tools, development systems, processes, and materials will help identify and plug the gaps to pave the way for HVM of 3D devices

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ST-Ericsson, CEA Leti, and Cadence have disclosed an application processor design known as Wioming (Wide IO Memory Interface Next Generation), the first application processor SOC integrated with a Wide I/O memory interface. Wioming integrates a Wide I/O DRAM memory stacked on top of two identical SOC logic die that incorporate multiple processor cores on each die

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Si2, in its 24th year, is an organization of “semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design.” Si2 represents over 90 companies involved in all parts of the silicon supply chain throughout the world.

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3D Integrated Circuit Packaging (3DIC): As shown in the Figure above, several 3D techniques are being developed, such as mounting ICs on a Silicon Interposer, Stacked Dies and Package on Package (PoP). Through Silicon Vias (TSVs) are

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At the recent RTI Architectures for Semiconductor Integration and Packaging (RTI ASIP), Raj Pendse, VP and CMO for STATSChipPAC (SCP) gave an in depth presentation on SCPs thoughts and approach to advanced packaging and 2.5/3D. i-Micronews thought it was worth A Closer Look…

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First of all, this standard is timely and very useful for 3D integration technology, especially for mobile products. Congratulations! Secondly, I read through all those 67 pages of the standard and didn’t see the words “through-silicon via or TSV”. I admire the authors’ principle, honesty and courage. After all, the objective of this standard is to specify the Logic/Memory Interface (LMI) and have nothing to do with TSVs! Sure, the memory cube and the logic/SoC may very well use TSVs, but it is out of the scope of this standard!

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In today's blog post, we'll look at TSV sizes for TSMC, IBM and others, and discuss technical reasons for the fat TSVs we are seeing... I'll present solutions to this issue at the IEEE CPMT Society on Wednesday

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It’s just one week into the year, I am increasingly getting the feeling that 2012 is going to be a momentous, tumultuous year for semiconductor technology and low-power system design. Among the many recent events that are giving me this feeling are the changes taking place in the NAND Flash arena

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3DIC presentations at the recent IEEE IEDM Conference focused on potential reliability concerns. ST Micro / Leti reported on two potential reliability issues for direct bond copper -- namely stress induced voiding and electromigration. Electromigration (EM) and stress-induced voiding (SIV) testing was performed on bonded daisy chains to investigate the reliability of the structures. Test vehicles were wafers bonded at room temperature, atmospheric pressure, and ambient air and then annealed at 200°C or 400°C to strengthen the bonding

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The supply chain was hit hard in 2011. It’s unclear whether 2012 will bring a reprieve. A cloudy global economic forecast is causing uncertainty among many corporations, even those in the electronics industry. While last year’s worries were caused by natural disasters, 2012 fears are man made.

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According to market of China's flashing memory Time sequence will enter 2012 years soon, semi-conductive industry's technology will improve continuously, among them 3D IC is the development trend of the chip in the future

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Micron Technology's Hybrid Memory Cube (HMC), a 3D IC with TSVs, is making use of IBM's 3D IC expertise. It will achieve speeds 15 times faster than today's technology in a 90% smaller package. IBM's fabrication facility is

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Perhaps no semiconductor company took it on the chin harder the last half of 2011 than Micron. And yet, perhaps no company was racing as hard as Micron to make a radical changeover. Micron is considered a bell weather on the overall health of the semiconductor industry given that DRAM, NAND and NOR Flash are used in some combination in every piece of electronic equipment. But sometimes economics and geopolitics come to the fore and, watch out, the DRAM market tanks. For Micron, the Future is not standard commodity DRAM, it is High Performance Servers and NAND Storage. Both have processor vendors as partners and some interesting innovation on the horizon

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Four groups within Semiconductor Equipment and Materials International (SEMI) are working on 3D IC standards. Its Three-Dimensional Stacked Integrated Circuits Committee includes SEMI members Globalfoundries,

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For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might get. I started thinking about the year’s major announcements and here’s my short list:

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Here is an article written by Javier DeLaCruz, eSilicon’s semiconductor packaging director. Javier is sharing his feeling on 3DIC for ASICs applications. “3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible.”

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The nascent 3D IC industry's foremost scribe, Francoise von Trapp, has just published a wrap up of this weeks 3D IC assembly conference held by the Research Triangle Institute in Burlingame, California. She notes some of

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When I was in high school and then in college, I used my mother’s Smith-Corona MANUAL typewriter to write all my English and journalism papers. (Yes, electric typewriters already existed, but we were "slow adopters" — aka "cheap" — heck, we didn’t even have a color TV until 1981) Those were the days of white-out, carbon paper, and lots and lots of revisions. Watching my high school-age daughters whip up their homework on their laptops, I can’t help but think how easy they have it.The same can be said for EDA tools designated for 3D TSV designs. As Mark Santoro, CEO of MicroMagic, developers of the world’s first layout editor for 3D IC, said to me, “You can use a manual typewriter to write your dissertation. It will take longer than using a word processor and you won’t end up with as good a product, but it can be done."

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Following the introduction of the wide I/O DRAM, further research and development of 3D IC technology will be driven by high demand, high volume applications that continue to demonstrate the benefits of 3D integration,

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Meeting: 3D IC Working Group Meeting Presentation: 2.5D and MEPTEC Update (PDF, 2.4 MB) Applied Materials Overview (PDF, 717 KB) Wide I/O Standard JC 42.6 (PDF, 822 KB) Date: December 12, 2011 Location Applied Materials, San

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We welcome back guest blogger, Paul Werbaneth, newly appointed business development manager at EV Group. Werbaneth's return to the pages of 3D InCites begins with a two-part blog post on his perceptions of the 2011 Global Interposer Technology Workshop

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I take my running shoes with me when I’m on the road, and during the poster session and nosh that followed Day 1 of the GIT Workshop at Georgia Tech I asked one of the presenting students about whether there were any famous runs at Georgia Tech

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The supply chain business model for manufacturing 3D stacked ICS has caused perhaps one of the hottest debates so far in commercializing 3D semiconductor processes. It’s easy to see why. Beyond the rather obvious question of who will own the liability of damaged devices, there’s a good deal of revenue at stake for those who make the investment in adding capacity for middle end of the line (MEOL) processes, whether they are a pure-play foundry, IDM or OSAT. At last week’s RTI 3D Architectures for Semiconductor Integration and Packaging (ASIP), we heard from TSMC, IBM , and STATS ChipPAC on their manufacturing readiness and arguments for the optimal hand-off point. We also heard recommendations from the research community as well as suppliers

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To get further reductions in package size and system power consumption and to get substantial boosts in system bandwidth, there's only one path forward: 3D IC assembly. According to the data gleaned from presentations by

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Yesterday, at the RTI 3D Conference, Pascal Vivet from CEA-Leti and Vincent Guérin from ST-Ericsson unveiled a 3D IC project that represents a real Tour de Force of cutting-edge system technology. The quest starts with a

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Day Two of 3D ASIP and even though the conference opened with declarations that “3D is here” it’s clear after attending the sessions and hearing what all the presenters have to say, that this is a multi-dimensional situation. First, there are the vendors and suppliers, who have a lot at stake, having invested billions developing processes to get to this point. Then there are the manufacturers — IDMS, Foundries, and OSATS —who see the potential and are investing in capital equipment to be ready when that first order comes; and lastly, but most importantly, there are the customers (fabless, fab-lite and end-users) who, at the end of the day, really cast the deciding vote as to whether (or more likely when) this goes or not

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3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

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According to Ken Shoemaker, Vice-Chair of the JEDEC 42.6 Low Power Memories committee, the Wide I/O specification has been finalized and approved by the directors. It will be published shortly. Participants in the effort included representatives from Elpida, Hynix, Micron, Qualcomm, TI, Intel, AMD, and Apple (and more but I couldn’t write them down fast enough)

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The two major FPGA houses — Altera Corp. and Xilinx Inc. — are bitter rivals in the market. Altera and Xilinx have different design philosophies and concepts. In the 2.5D/3D chip world, Xilinx has already announced its first 2.5D FPGA. Altera is working on unannounced 3D-like devices in the lab

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Got up before dawn to catch the 6am flight to SFO for RTI’s 3D Architectures for Systems Integration and Packaging Conference (3D ASIP), and arrived just in time to catch the tail-end of Xilinx’ Ivo Bolson’s presentation. It was ironic (or strategic?) that Ivo started things off, because it was just a year ago that Xilinx 2.5D was the big story at 3D ASIP and became the poster child as the first step to 3D integration. So it was fitting that Bolson’s comments set the stage for the rest of the day’s presentations

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Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That's easy to understand. It's not at the moment. Yet I do believe in the inevitability of 3D assembly. Here's why. At last week's IEEE

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My head is spinning. I just spent a few hours reading through all the latest 3D technology posts on various semiconductor news websites; something I find myself doing a lot more ever since I took on 3D-ICs.com. As editorial director of that site, it’s my job to sift through all the RSS feeds and aggregate all that is 3D through the portal site

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Word on the street is, if 3D is serving a niche market, it’s going to be a big niche! At least that was what Subramanian Iyer reported back from the 3D Panel he moderated on December 6 during IEDM 2011. The panel’s ultimate goal was to address the overall theme "Is 3 Dimensional Integration at Best a Niche Play?”. Organizers tested a new format, leaving the powerpoint slides at home, and getting right to the discussion. Iyer declared it to be a great success, with attendees numbering in the neighborhood of 400, lots of lively discussion among the panelists and involvement from audience

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I’m attending the all-day workshop on 3D ICs being held by the local IEEE Chapter of the CPMT (Components, Packaging, and Manufacturing Technology) Society and it’s a huge success with 150 attendees. I’m busy listening to presentations, but here’s a photo I just shot from the auditorium at TowerJazz Semiconductors

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During the recent (December 2011) IEEE CPMT Orange County 3D workshop, Eric Beyne of IMEC offered his look at 2.5D/3D challenges and progress. I-Micronews thought it deserved “A Closer Look”

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For some time, the MEMS foundry business has been dominated by one vendor — STMicroelectronics Inc. — followed by a steep drop in share by the likes of Texas Instruments Inc., Sony Corp. and a plethora of smaller MEMS-only foundry players

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I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)” and “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”) Now Deepak Sekur, Chief Scientist at Monolithic 3D, has written his own blog titled “Is the Buzz around Xilinx’s 2.5D FPGA Justified”

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When: Monday, December 12, 2011 10:30 AM-1:30 PM (UTC-06:00) Central Time (US & Canada). Where: Applied Materials Note: The GMT offset above does not reflect daylight saving time adjustments. *~*~*~*~*~*~*~*~*~* 3D IC Working Group

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The Xilinx 2.5D FPGA has met with widespread acclaim since its launch in October 2010. EETimes called it "the world's highest capacity FPGA". Two of my favorite bloggers, Steve Leibson and Francoise von Trapp, had positive things to say about it too. Steve dubbed it "generation-jumping" and Francoise said "it has got the 3D IC market segment abuzz". Since I specialize in this field, people frequently ask me about pros and cons of 2.5D FPGAs, and want to know if the press attention is justified. Thought I should write a blog-post on the subject today.

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The Hybrid Memory Cube consortium formed by Samsung Electronics and Micron Technology this October is leveraging IBM Microelectronics' 3D wafer-baking expertise to get HMC memory to market in two years

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Next month’s DesignCon 2012, which will take place in Santa Clara, CA, will host many interesting panels, including “Why do we need 3-D design standards?” As cutting edge and exciting as that title sounds, it may be asking the wrong question, however. The right question may be, Do the economics of 3-D make sense, and who takes the fall when things go wrong?

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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has an exciting energy level missing in other forums. Beyond the greeting of old industry friends and colleagues, there was true participation and engagement. This was demonstrated in numerous ways from the dialogue between speakers and audience during the presentations to the in-depth discussions in the packed exhibit hall

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In this post, guest blogger, John H. Lau, Industrial Technology Research Institute (ITRI) in Taiwan unravels the mysteries of Wide I/O devices. There is much confusion among Wide I/O Memory, Wide I/O DRAM, Wide I/O Interface, and Memory-Chip Stacking. The objective of this brief note is to group them together, show their applications, and tell you a very “simple” story with samples, not just Power-Point Engineering (PPE) or analysts’ rumors! Figure 1 shows the PPE of these 4 memory structures related to TSV and 3D IC integration. Please be noted that 3D Si integration is out of the scope

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Interest in silicon interposers, or “2.5D” as ASE’s Ho Ming Tong named them a few years ago, has certainly increased over the past few years and has culminated with the commercialization of the Xilinx Virtex-7. I-Micronews felt it was time to step back and take a “Closer Look”.

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The most under-appreciated members of any embedded systems design team may be the packaging specialists. Until I read two recent contributions to Embedded.com: “Xilinx’s Virtex-7 200T FPGAs” by Jack Ganssle, and “3D-IC Design” by Samta Bansal, I was not completely aware of the daunting challenges packaging designers face and how much coordinated effort is required between all team members.

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Last week, silicon-interposer foundry Deca Technologies unstealthed. I found out from an article in the San Jose Mercury News and just published a blog about the announcement in my other blog, the EDA360 Insider. Deca is a subsidiary of Cypress Semiconductor and the outspoken President and CEO of Cypress, TJ Rodgers, was good for a quote, as always:

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Two weeks ago, wearing my Chip Scale Review Sr. technical editor hat, I attended (along with 11 other journalists) an exclusive press conference launching a new electronic interconnect company, Deca Technologies, which claims to have developed disruptive manufacturing processes based on its sister company, SunPower’s, solar cell wafer processes, rather than traditional semiconductor manufacturing processes, that reportedly result in a drastic reduction in cycle time and cost, and offers unprecedented design-to-product flexibility

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Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D

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Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D

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Home > ADVANCED PACKAGING: 3D IC, WLP & TSV > MEMSIC presents smallest MEMS Accelerometer in 3D WLP packa... > ADVANCED PACKAGING: 3D IC, WLP & TSV. Nov 15th, 2011. MEMSIC presents smallest MEMS Accelerometer

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But as the world moves toward the 2.5D and 3D chip era, the lines in the IC manufacturing flow are blurring. Within these emerging segments, the chip “supply chain model is under stress,” said Rich Rice, senior vice president

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3D ICs Have a History. Steve's Improbable History of 3D ICs? Six decades of 3D electronic packaging | EDA360 Insider is a great quick history (with pictures!) of 3-dimensional chips (actually, going back to the vacuum tube

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3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were extended by Mentor Graphics for the Calibre tool to handle TSV (Thru Silicon Via) technology. This extension is called Calibre 3DSTACK

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I had a bit of an “aha!” moment yesterday at the MEPTEC 2.5D, 3D and Beyond Conference, with regard to the whole supply chain conundrum that seems continues to be part of the 3D commercialization hold-up. After listening to Sunil Patel of GlobalFoundries and Rich Rice of ASE discuss their respective companies’ game plans, it hit me. Perhaps there IS more than one way to skin this particular cat. (God – that’s an awful cliché isn’t it? It’s much harsher in text form than verbal… but I digress)

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The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain

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My first panelist to speak on last week's 3D IC panel at the 9th International SoC Conference in Newport Beach was Herb Reiter, generally known as “Mr. 3D.” Herb knows everyone in the industry connected to anything 3D.

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Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today's state of the art for 3D IC development. I will be blogging the presentations made by the

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Despite its high potential, a lack of uniform standards have slowed the migration of 3D technologies into mainstream production. In particular, cost-effective high-volume 3D integration of ICs from multiple sources will require the development of a cohesive set of end-to-end standards at the interfaces between supply chain partners

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Ever since the TSMC OIP Forum where Dr. Shang-Yi Chiang openly asked customers, “When do you want 3D Transistors (FinFETS)?” I have heard quite a few debates on the topic inside the top fabless semiconductor companies. The bottom line, in my expert opinion, is that TSMC will add FinFETS to the N20 (20nm) process node in parallel with planar transistors and here are the reasons why:

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This has to be the 3D IC educational bargain for this year. The Orange County Chapter of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society is sponsoring an all-day workshop on 3D IC

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Earlier this week Invensas Corporation, a wholly-owned subsidiary of Tessera Technologies, Inc., announced both its acquisition of ALLVIA’s patent assets, and a two-year collaborative partnership with ALLVIA to further develop technology and intellectual property (IP) in the 3-dimensional integrated circuit (3D-IC) packaging space. This strategic alliance is expected to optimize the strengths of each company at a time when 2.5D and 3D ICs are poised for market adoption. I spoke with Simon McElrea, president of Invensas Corporation, and Sergey Savastiouk, chief executive officer, ALLVIA, Inc. to learn more about the motivations and benefits of this for this acquisition/collaboration

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Final Program of 3D IC Workshop now available. Posted on October 31, 2011 by ocs-cpmt. The final program of the CPMT OC Chapter All-Day 3D IC Workshop on Dec 9, 2011 is now available. Please see the final announcement flier for more

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Through-Silicon Vias (TSV) Technology for Smart 3D-Package IC Integration. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as System in Package, Chip Stack MCM,

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Through-Silicon Via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. In TSV wafers or the chips are stacked on top of each other, and are connected using vertical pathways of interconnects (instead of wires) that run completely through the chips. The chips can be of the same type or of different types, referred to as homogeneous or heterogeneous integration, respectively

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Through-Silicon Via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. In TSV wafers or the chips are stacked on top of each other, and are connected using vertical pathways of interconnects (instead of wires) that run completely through the chips. The chips can be of the same type or of different types, referred to as homogeneous or heterogeneous integration, respectively

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ADVANCED PACKAGING: 3D IC, WLP & TSV. Nov 1st, 2011. Micron / Samsung TSV stacked memory collaboration: a closer look. Samsung Electronics and Micron Technology have created an industry group to collaborate on the

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ADVANCED PACKAGING: 3D IC, WLP & TSV. Nov 1st, 2011. Micron / Samsung TSV stacked memory collaboration: a closer look. Samsung Electronics and Micron Technology have created an industry group to collaborate on the

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Last week, I read a very interesting report from SEMICON Europa concerning the cost of development for 450mm reaching between $20 and 40B ; and that this could force a choice between funding 450 and funding More than More(including 3DIC) developments

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Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, 36 12.5Gbps GTX serial transceivers, and 1200 user I/O pins. All in about 20W (!!!). The only fly in the ointment, if you want to call it that, is that no one on this planet can make this FPGA as a monolithic device. The Virtex-7 FPGA is a 2.5D assembly that combines four FPGA tiles on a silicon interposer

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mproved stepping accuracy: The first and most obvious requirement for micro-bump/TSV probing is for accurate die stepping. From our customers we estimate we should be prepared to probe at 40 um pitch next year, and at 20 um pitch (with 5 to 10 um pads) around 2014. The full accuracy budget is not yet entirely clear, but to accurately hit 5 to 10 um pads, we expect the prober accuracy should be within 1.5 um for 40 um pitch probing, meaning that the combined effect of probe station move accuracy and probe-to-pad-alignment assures that a “perfect” probe tip array will contact a “perfect” pad array within that XY tolerance. We expect the requirement will be less than 1 um for 20 um pitch probing. Early results indicate this is achievable, at least at room temperature

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EPworks was founded to provide advanced 3D semiconductor packaging solutions. They have expanded from their initial focus on 3D TSV research activities into providing state-of-the-art 3D interposer and stacked IC

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Guest Blogger, John H. Lau, of ITRI, is back again with some thoughts on Nanotechnology and 3D Integration's history and thoughts on the future. Enjoy! ~ F.v.T. In the evening of December 29th, 1959, the 1965 Nobel Physics laureate Richard Feynman gave a lecture with the title “There's Plenty of Room at the Bottom” to the American Physical Society at CalTech

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Friday was the first day to get your hands on an Apple iPhone 4S. I saw a photo in the San Jose Mercury News of Steve “Woz” Wozniak sitting in a lawn chair camped out at a local Apple store. He was queued up first in line to pick up one of the new phones. Meanwhile, there are several engineers around the world busily tearing apart their copies of the iPhone to give you a peek at the innards. You can see examples of this teardown work on the Chipworks and iFixit Web sites. More including 2 3DIC devices

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Keywords: 3D chips TSVs IC manufacturing Chip makers have spent the past several years perfecting the through-silicon vias ( TSVs ) that will interconnect 3D IC

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Design-for-test and test engineering professionals throughout the entire semiconductor industry are preparing for 2.5D- and 3D-SICs (Stacked Integrated Circuits) to become product reality, with recent product announcements from a number of leading semiconductor companies, foundries, and assembly houses as public testimonials. Consequently, after experiencing a successful launch in 2010, the second edition of the 3D-TEST Workshop (in full: “IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits”), grew by 30% in 2011 to 129 attendees. Like last year, the 3D-TEST Workshop was organized in conjunction with the IEEE International Test Conference (ITC), the world’s premier test conference, and took place on September 19-23 at the Disneyland Hotel in Anaheim, California. Guest Blogger, Erik Jan Marinissen, imec, is the founder and Program Chair of this young and popular workshop. Here is his report on this year’s event

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A unified chip/package/module co-design methodology can address a number of analog and digital design integration issues. These challenges include the best placement of die I/O buffers and die bumps for optimal floorplanning; sufficient spacing between the die footprints in a package; and interconnect parasitics that are not so high as to cause signal integrity problems for critical signals.

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3D ICs complicate silicon testing, but solutions exist now to many of the key challenges. - by Stephen Pateras The next phase of semiconductor designs will see the adoption of 3D IC packages, vertical stacks of multiple bare die connected directly though the silicon. Through-silicon vias (TSV) result in shorter and thinner connections that can be distributed across the die. TSVs reduce package size and power consumption, while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. But TSVs complicate the test process, and there is no time to waste in finding solutions. Applications involving the stacking of one or more memory die on top of a logic die, for example using the JEDEC Wide I/O standard bus interface, are ramping quickly

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It is reported that the TSMC manufactured A6 chipset will incorporate 3D IC technology. It has also been reported that TSMC is in production with 3D IC technology and is in a race with Intel to manufacture a 3D IC chip. EETimes reported that

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There is a big difference between TSV type 3D IC and what I am talking about – monolithic 3D (10000x vertical connectivity)! With monolithic 3D IC every folding is equivalent for 1 node of scaling from every point one look at.

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Home > ADVANCED PACKAGING: 3D IC, WLP & TSV > Successful Semiconductor Fabless 2011 Event in Paris !... > ADVANCED PACKAGING: 3D IC, WLP & TSV. Sep 1st, 2011. Successful Semiconductor Fabless 2011 Event in Paris !

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Leading industry leaders to envision the future of 3D-IC at SiP Global Summit Taipei, Taiwan – August 11, 2011 – Given the growing importance of packaging and testing in the global semiconductor supply chain, SEMI will

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There are still lots of issues to work out and improve, but thermal management is getting lots of attention and progress is being made

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Reading Richard Goering's blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass

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Network with Cadence technologists and peers in the Cadence Community. Stay abreast of technology trends, news and opinion through Blogs, forums, and social networking

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While we wait for Lion, interesting to note the next Apple A6 processor will be made by Taiwan Semiconductor Manufacturing Co. (TSMC) and will be a 3D IC 28-nanometer low-power powerhouse, sweetly tucked away inside

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Effectively testing of stacked die will become one of the biggest challenges in 2.5D and 3D, but a methdology is in place to make this work

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MonolithIC 3D Inc., one of the industry?s leading innovators in 3D-IC technology, has unveiled a monolithic 3D DRAM technology. The startup claims this technology can provide a 2x-3x increase in memory density over

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MonolithIC 3D Inc., one of the industry?s leading innovators in 3D-IC technology, has unveiled a monolithic 3D DRAM technology. The startup claims this technology can provide a 2x-3x increase in memory density over

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SAN JOSE, Calif., July 8, 2011 -- (PRNewswire) -- MonolithIC 3D, Inc., the innovator of practical monolithic 3D IC technology, has unveiled multiple 3D IC technologies that now cover most mainstream semiconductor device types

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According to a press release, MonolithIC 3D – a association focused on 3D-IC record – denounced a new monolithic 3D DRAM record to yield increasing memory firmness during allied costs. As a provider of semiconductor

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Startup Announces Monolithic 3D DRAM Technology San Jose, CA (PRWEB) July 01, 2011 MonolithIC 3D Inc., one of the industry's leading innovators in 3D-IC technology, has unveiled a monolithic 3D DRAM technology

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The new 32GB RDIMM with 3D TSV package technology is based on Samsung's 30nm-class four gigabit (Gb) DDR3. It can transmit at speeds of up to 1333 megabits per second (Mbps), a 70 percent gain over preceding

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Japanese memory manufacturer Elpida Memory, Inc. (TYO: 6665) has just started sampling some very advanced memory modules

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The picture that came along with the press release makes it look like the chips are simply being simply glued together without any indication of the 3 prerequisites for 3D IC stacking, namely 1) thinning, 2)TSV and

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You can read an excellent new article on test challenges for 3D IC design here. The article was written by Samta Bansal of Cadence and Herb Reiter, Chair of the GSA's 3D-IC working Group. The article discusses the key

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Singapore-based IC distributor Serial System plans to issue 28 million TDRs (Taiwan depositary receipts) on the Taiwan Stock Exchange (TSE) on October... Read more · FCCL maker Asia Electronic Material looks to revenue

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While we wait for Lion, interesting to note the next Apple A6 processor will be made by Taiwan Semiconductor Manufacturing Co. (TSMC) and will be a 3D IC 28-nanometer low-power powerhouse, sweetly tucked away inside

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Sonics CEO Grant Pierce looks at what needs to change in SoC design, what's driving those changes, and how all of this will be affected by 2.5D and 3D stacking

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The picture that came along with the press release makes it look like the chips are simply being simply glued together without any indication of the 3 prerequisites for 3D IC stacking, namely 1) thinning, 2)TSV and

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Full 3D ICs will require extensions in methodology beyond what we have for 2.5D

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NAND as we know it is reaching the end of the line. It’s been a good run. But Judgement Day is Coming!

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There are still big advantages to be gleaned from 3D IC-packaging technology that's more than 30 years old. But there's a second, really subtle application of 3D assembly that you might possibly miss so I want to highlight it.

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Home > ADVANCED PACKAGING: 3D IC, WLP & TSV > Betting on through silicon vias in glass substrates... > ADVANCED PACKAGING: 3D IC, WLP & TSV. Sep 28th, 2011. Betting on through silicon vias in glass substrates. There are two big

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ADVANCED PACKAGING: 3D IC, WLP & TSV. Sep 23rd, 2011. Package innovation from STMicroelectronics shrinks antenna couplers to improve connection reliability and battery life. STMicroelectronics has unveiled two new chips for

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Semiconductor design is starting to see the adoption of 3D IC packages. These packages involve stacking multiple bare die vertically using connections that go directly though the silicon. Through-silicon vias (TSV)

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I knew we were onto something when Leo Archer and I chose 3D ICs and 3D packaging as the top of focus two and a half years ago when we first launched 3D InCites. The intention was to play off the word “incite” was to stir up interest in this emerging area of technology, while also capitalizing on the I C in the word InCites. Clever, no? Not everyone gets the name, (many think the name is 3D InCITIES) but most everyone gets what we’re about. As we draw closer to market adoption, there is more focus then ever industry wide on 3D integration, and I like to think maybe we had something to do with that

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Berlin/Brussels - September 30, 2011 – 3D-IC, new device architectures, next-generation lithography, advanced materials, and 450mm are among the technical topic highlights to be featured next month at SEMICON Europa 2011, October

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I got an email last week from R. Colin Johnson, of EE Times, looking for my impression on the collaboration between IBM and 3M, and their announcement to begin development of an adhesive material that would allow building “silicon towers” or “silicon bricks” that would be 100 chips high. Johnson wanted to know my thoughts on this, could 3M’s thermally conductive adhesive really be, as they claimed, the “key material” for the commercialization of multi-chip 3D ICs

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As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area.

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I still believe performance is driving the business. Unfortunately, those fancy technologies are crucial to the semiconductor industry but we don't get recognition. People don't care about a 3D IC. They care about being able to

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ADVANCED PACKAGING: 3D IC, WLP & TSV. Oct 7th, 2011. Qualcomm sees pricing challenges for TSVs. The development of three-dimensional (3D) chips based on through-silicon-vias (TSVs) is making solid progress on the technology

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Home > ADVANCED PACKAGING: 3D IC, WLP & TSV > The Intel “Tri-Gate Transistor” structure: a closer look... > ADVANCED PACKAGING: 3D IC, WLP & TSV. Oct 4th, 2011. The Intel “Tri-Gate Transistor” structure: a closer look. At the most

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I just got back from the IWLPC 2011 in Santa Clara, and my head is full of commentary just begging to be dumped on a page. This year’s agenda was jam packed with 3D discussion — plenary talks by Matt Nowak of Qualcomm and John Lau of ITRI, a panel on 3D infrastructure, and the 2.5D/3D debate — which was great for me and the rest of the 3D InCites community, but I kind of felt bad for the MEMS and WLP folks, because beyond technology tracks devoted to MEMS and WLP, most of the ‘extra’ events focused in the 3D technology space. But then again, I guess 3D really does touch on MEMS and WLP as well, so maybe it’s just indicative of the direction the semiconductor world is going

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I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper published in 2007 by researchers from the University of Washington in Seattle and the University of Michigan in Ann Arbor. Essentially, the “mortar” is a silicon interposer, which may or may not have active elements on it. The bricks are small, single-function chips bonded to the interposer. In this way, you can assemble a more complex chip using a variety of IC process technologies as appropriate for each “brick.”

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