These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below

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From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here's why: We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit

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Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly

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Imec's Luc van den Hove vs. Intel's Mark Bohr. Picture. We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses EE Time's article about: "Moore's Law seen hitting big bump at

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MonolithIC 3D Inc. is an IP company with operations in Silicon Valley, Romania and Israel. It invented and developed a practical path to the monolithic 3D Integrated Circuit, which includes multiple derivatives for Logic,

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3D NAND Opens the Door for Monolithic 3D. 10/01/2012. 7 Comments. Picture. We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses the opportunities of 3D NAND with

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We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC. For those who could not make it, here is what our booth looked like: Picture. Nice tie

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Yes, unless we Augment Dimensional Scaling with monolithic 3D-IC Scaling. Picture. We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Cost Reduction

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Intel vs. the Foundries: where is advanced logic heading? 06/04/2012. 3 Comments. Picture. We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about Intel vs. Foundries

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Download the "Monolithic 3D - In General" ebook for FREE. Read and write reviews and more

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Dimension Scaling and the SRAM Bit-Cell [...]

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Toshiba is expected to continue being the largest semiconductor firm in Japan. The firm plans to begin the volume production of NAND flash using the 15-18nm technology in 2013 and develop 3D NAND flash technologies

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“On the technology and operations front, we are making steady technical advancements with both our planar and 3D NAND technologies. We began shipping our 20nm TLC NAND flash and continued to increase our 20nm

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Predicting this is fraught with uncertainty but SanDisk have been quoted as saying that there are two nodes left for conventional planar NAND (1Ynm later this year and 1Z next year). At that point, 3D NAND is seen as the

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David Fuchs at Hephastus Project outlines what kind of computing would be possible with 25 nanometer 3D Nand bricks. A one inch cube could hold 1,000,000,000,000,000,000 of these 25 nm bricks. Using two simple

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Software becomes nothing more than the configuration of the 3D NAND array. This removes a huge amount of overhead, allows optimization in ways that can not be done on standard computer systems, and speeds up

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On the technology and operations front, we are making steady technical advancements with both our planar and 3D NAND technologies. We began shipping our 20-nanometer TLC NAND flash and continued to increase our

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IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended at San Francisco last week, and the issue of dimension scaling as it relates to EUV and future per transistor device cost was an important item in the plenary session. But the issue of scaling as it relates to the SRAM was an important item in many of the session as we will farther discus herein

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With new application wins in NAND flash, improving prices and higher utilization rates, the company is seeing positive momentum. Additionally, Applied anticipates higher spending this year for building the 3D NAND

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Mass storage markets served by flash NAND could begin using 3D RRAM in 2017-2018, when 3D NAND will slow down its scalability as predicted by all of the main memory players. When this happens, a massive RRAM

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OCZ Technology Group, Inc., a leading provider of high-performance solid-state drives (SSDs) for computing devices and systems, today announced a new 20 nanometer (nm) NAND flash version of its award-winning Vertex

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According to Micron, “The P400m takes full advantage of Micron's vertical integration with XPERT and a custom MLC NAND device designed specifically for our enterprise SSD product line. This NAND device is built using our

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[...]

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"Innovations for Next Generation Scaling" We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Common Platform Technology Forum 2013

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Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., San Jose, CA, blogs about the evolution of 3D technology seen at the International Electron Devices Meeting. From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:

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Charge Trap and Three-Dimensional (3D) NAND In order to continue to scale NAND Flash, the industry is evaluating two possible ways to scale below the 20 nm level: 1) Three-Dimensional cell; and 2) planar cell, such as

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A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical

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Samsung has got involved in the development of three-dimensional realization of memory ReRAM (or VRRAM – vertical ReRAM) in order to finally find a replacement for bad NAND-memory. In general, the technology

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In addition, the company continues to explore new types of NAND flash memory, including 3D NAND flash and 3-bits-per-cell NAND flash. “We continue to be pleased with our solid-state drive business as these shipments

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electronics.wesrch.com - Papers - NAND Scaling Challenges, High Tech. ... Nand Scalling Challenges ... Node 1Ynm Meeting the Challenge 3-Pronged Strategy to Meet the Technology Challenge 3D Resistive RAM (ReRAM) NAND Scaling BiCS 3D NAND Demand for Storage Adding the 3rd Dimension: BiCS and 3D Crosspoint BIT COST SCALABLE (BICS) 3D CROSSPOINT RESISTIVE RAM 3D NAND 3D RRAM > Existing NAND Toolsets > Vertical NAND Strings

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Tech., 2009 After our BiCS proposal, various 3D NAND cells have been proposed. BiCS has smaller cell size, simpler process and better disturb immunity. BiCS is the most promising 3D Flash memory. 33 Expansion of BiCS

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"According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata." Ron Maltiel

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An interesting and potentially useful discovery by ROM manufacturer Macronix has uncovered a new method that could give NAND Flash Memory a longer lifespan of 100 million cycles. ... USB Toy 3D Webcam from Thanko

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Thanks to everybody who came to IEDM this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei of Stanford University. You can find the meeting paper and slides here

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Samsung Electronics Co Ltd developed a memory cell technology for realizing a 3D ReRAM (resistive random-access memory) whose capacity is larger than that of NAND flash memory. The new technology realizes a

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"According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata." Ron Maltiel

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Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn't get to in the first two posts, which I'll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory

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The most likely replacement for NAND flash, however, continues to be 3D stacked flash memory. Micron and Intel, SK Hynix and Macronix will all talk about their work on 3D NAND. 2. EETimes has an IEDM preview as well

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There are a couple of notable updates circulating this week involving companies in the 3D space. The first I saw was news from Sony that it has introduced its next-generation CMOS Image sensor they claim is “ the industry's smallest, CMOS image sensor and camera system”.

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“Flash wears out after being programmed and erased about 10,000 times,” said the IEEE Spectrum. Engineers at Macronix have a solution that moves flash memory over to a new life. They propose a “self-healing” NAND flash

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SanDisk Doesn't Show Up in NAND Market Share Figures Every so often I run into someone who asks about the discrepancy between various analysts' NAND market share rankings and SanDisk's shipments. After all

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... announces updates to developer ecosystem programs · Acquiring Sony battery biz will help Foxconn strengthen vertical integration · Taiwan market: Taiwan Mobile launches cross-platform mobile streaming video services

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Moving to a vertical crosspoint array is vastly simplified by the lack of a need for a select device and eliminates the need for (currently) costly minimum feature lithography. ... As he described in his Flash Memory Summit presentation, PCRAM is not inherently fast enough for main memory (DRAM replacement) and while it is faster than NAND, it cannot combine the density (smallest cell size) and speed of ReRAM for data storage (NAND replacement). PCRAM requires

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MonolithIC 3D Inc. was established in 2009 by Dr. Zvi Or-Bach, a well-known Silicon Valley serial entrepreneur, as NuPGA. The NuPGA's mission was to develop programmable logic technology with density, speed, and

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Post by Chris Mellor (thank you) over at El Reg – Good background information on the NAND technologies pitfalls The NAND flash industry is facing a process size shrink crunch and no replacement technology is ready. Unless 3D die stacking works, we are facing a solid state storage capacity shortage. The NAND flash foundries are…

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3D NAND flash is coming. Posted by admin on November 15th, 2012. Brian Bailey writes : Flash memory has very quickly risen from being an obscure memory type to perhaps becoming the dominant memory type for many devices, including

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On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intel’s revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm

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During the exhibition, Macronix will present its 3D VG (Vertical Gate) NAND Flash using its patented BE-SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture. Traditional NAND Flash will be

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Historically, manufacturers have increased memory density by packing more cells together in a single plane. As traditional dimensional shrinks become increasingly difficult, the industry is transitioning from planar to 3D NAND

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Glass interposers got a thumbs up from i-MicroNews in a “Closer Look” post reviewing Corning’s Peter Bocko’s presentation at IMAPS 2012. Based on work done as part of Ga Tech’s consortium, Bocko demonstrated that “glass interposers show less warp during chip assembly, faster signal propagation and significantly reduced signal loss. In fact they found a 10x lower signal loss in glass for a 6x longer interconnect. Such a 60x lower leakage improves power efficiency,”

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The semiconductor industry is in the doldrums. The PC market shrinks, Intel shares sink, Applied Materials cuts staff, and even Apple suddenly experiences its share price drop by $100 in a month. Are things really so bad?

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The adoption rate of Solid state disks is fast and they are getting faster and faster. To gain higher volume sizes the NAND ICs need to shrink and that could pose an issue in the near future. Shrinking the die sizes of flash

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[...]

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In one possible scenario in the next five years (or longer), a next-generation MRAM called spin-torque MRAM (STT-RAM) is the candidate to replace DRAM and SRAM. Also in the distant future, 3D NAND and ReRAM may

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NAND as we know it is reaching the end of the line. It's been a good run. But Judgement Day is Coming! 2014 looks like the year. Not so far off. 3D NAND looks like the technology ready to pick up where 2D NAND leaves off

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Kilopass describes today its new embedded VCM (Vertical Cross-point Memory) NVM IP bit cell. The new VCM bit cell quadruples the density of today's anti-fuse ... By comparison, a typical embedded flash memory has an area of about 50 F2, and the state-of-the-art NAND flash bit cell with a fully customized memory process technology and extra cost can only achieve 6F2, about half of the area of the VCM bit cell. The VCM bit cell is the densest eNVM that exists in

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As a result NAND flash manufacturers are increasingly focusing on vertical integration, or ways to develop partner ecosystem, to provide complete SSD solutions for embedded and server applications. Posted by Gupta at 2:00

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The ability to create vertically stacked memory bits used in 3D NAND devices, expected to replace the planar NAND memories in the next few years, leans heavily on precise etch capabilities. Applied Materials today (June 27)

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Plasma etch has never been as challenged as it is today by the transition from planar NAND flash structures to 3D. The incredible cost-per-bit reduction of NAND that has made smartphones and tablets economically viable

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Consequently, there's a quest for developing 3D NAND Flash cell structures, which greatly expand the volumetric capacity of the bit cell's floating gate. Park showed a slide with four proposed 3D NAND cell designs from

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3D NAND structures could help with the scaling problem, Park suggested. He briefly reviewed several proposed 3D NAND structures including the Toshiba p-BiCS, Samsung TCAT, Hynix 3D FG, and Micron architectures

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While it still has a couple nodes of life left in it, predictions for its demise finally appear to be true; options include 3D NAND as well as number of more exotic solutions

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About a year ago, I wrote an EDA360 Insider blog entry about 3D NAND Flash semiconductor memory. (See “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron”) In this post, I discussed a talk by Glen

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According to a folks during Applied Materials, perplexing to build 3D NAND structures in genuine life would be like perplexing to puncture a one-kilometer-deep, three-kilometer-long ditch with walls accurately 3 meters apart,

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It will improve system performance and the user experience for a wide variety of applications including web browsing, 3D and HD video capture and playback, multi-tasking activities, augmented reality and the use of social networking sites and interactive graphics-rich gaming. The ultra high-speed ... The new eMMC's fully managed NAND memory comes with its own high performance controller and intelligent flash management firmware. To meet the market need for

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In a surprise announcement Toshiba has said that it will immediately cut NAND flash production by approximately 30%. The company explains that this is being done “to reduce inventory in the market and improve the overall

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Throughout the past month, Max Maxfield, Editor in Chief of All Programmable Planet, has been examining 3D ICs, past, present and future, in a noble attempt to make sense of the confusion. The result turned into a blog post trilogy that does just that. Here’s a summary of each post that together provide a comprehensive primer of 3D ICs. If you book mark THIS page, you’ll have a useful resource for easy reference

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Electrical engineers at The University of Texas at Arlington and at the University of Wisconsin-Madison have devised a new laser for on-chip optical connections that could give computers a huge boost in speed and energy efficiency

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Applied Materials has taken the wraps off a new etching system meant to turn vertically stacked, three-dimensional transistors from lab experiments into commercial reality. The new Centura Avatar solves multiple problems facing manufacturers who are interested in 3D NAND but find their current equipment not up to the task of actually building it. While we’re specifically talking about 3D NAND today, a number of the challenges to scaling flash memory apply to scaling CPU logic as well

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Applied Materials has been showing off its new etching system which it claims can create vertically stacked, three-dimensional transistors. The Centura Avatar process is supposed to fix problems facing manufacturers who are interested in 3D NAND.

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It might be the understatement of the year to say that Flash memory is popular. Every year, we consume nearly twice as many bits as the year before

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IPDiA, a leading supplier of silicon passive components and 3D silicon packaging is offering what is probably the first call to participate to a Through Silicon Via (TSV) Multi Part Wafer (MPW) or so-called “pizza mask”. Through

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Yes, unless we Augment Dimensional Scaling with monolithic 3D-IC Scaling [...]

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I've been meaning to write about a comment regarding NAND Flash memory and SSDs written by Thomas McCormick in LinkedIn's Solid State Storage Group and this seems like the perfect time. McCormick is an Integrated

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The two other industry leaders awarded for Silicon and Strategies (respectively) were Zvi Or-Bach, CEO of MonolithIC 3D, and Dr. Kwok Wu, Head of Embedded Software and Systems at Freescale Semiconductor. The top

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The Stanford engineers have demonstrated their technique by developing sequential storage and arithmetic circuits and a monolithic 3D integrated circuit. Source: http://engineering.stanford.edu/. Latest News

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Low Profile 3D Silicon Capacitors for Embedded Technology (100μm Thickness). It is a well known fact that standard passive ... Greenliant Now Shipping Industrial Grade SATA NAND... Greenliant Systems Appoints Avnet

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“Despite vertical stacking, the lateral scaling of 3D NAND flash is critically important because otherwise more than 16 stacking layers are needed to be cost competitive to 20nm 2D NAND,” the Macronix researchers claim

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... Flash Industry, Enterprise Servers & Storage, Solid State Drives, NAND Industry Bit Growth Moderating, Supply And Demand Harmony, NVM Continues Beyond NAND, Adding the 3rd Dimension: BiCS and 3D Crosspoint

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After seeing the latest press release on Ziptronix foray into the memory space, I sought out Kathy Cook, business development manager at Ziptronix, at ECTC to get the full story. We’ve been reading and hearing a lot about Ziptronix ZiBond process being used in CMOS image sensor (BSI) technology, and particularly in its recent partnership with Sony for CIS with backside illumination (BSI). ZiBond is the name of the company’s patented room temperature direct oxide bond technology. The latest announcement involves the company’s second product, direct bond interconnect (DBI), which is an extension of the ZiBond process that forms actual interconnects between die with or without through silicon vias (TSVs).

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Ever since the “Intel Reinvents Transistors Using New 3-D Structure” PR campaign I have been at odds with them. As technologists, I have nothing but respect for Intel. The Intel PR department, however, quite frankly, is evil. Correct me if I’m wrong here but Intel did not “reinvent” the transistor. Nor did they come up with the name Tri-Gate. If not for prior art, Intel would certainly have trademarked it, my opinion

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A lot of turmoil recently arose over the lack of TSMC capacity to support the 28nm logic ramp. Some of the larger TSMC customers such as Qualcomm and Nvidia made public their disenchantment with TSMC’s delivery of 28nm products.

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The word around Silicon Valley is that Intel is having manufacturing issues at 22nm. The first indication is product launch delays, but more importantly, the dissection of the 22nm silicon. The conclusions being made are:

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Last year EE Times ACE annual innovation awards Zvi Or-Bach think 3D IC designers need from the silicon through-hole technology transition to super high density monolithic 3D technology. BeSang Inc claims being made

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At present the most advanced technology should be used silicon through-hole3D chips are stacked,AM2140-10JC price, almost leading semiconductor companies are working on the technology

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A Highly Pitch Scalable 3D Vertical Gate (VG) NAND Flash Decoded by a Novel Self-Aligned Independently Controlled Double Gate (IDG) String Select Transistor (SSL), C.-P. Chen et al., Macronix International, Ltd

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about the latest news regarding the reversal of the trend from Foundry model back to the IDM model.

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Qualcomm has been working on 3D IC technology development projects to help prepare the company for a 3D future. “3D DRAM stacking has started—it's shipping in products because it has maintained the bit density/cost

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The 2012 Symposia on VLSI Technology & Circuits, planned for mid-June in Honolulu, points to future directions in memory technology, including 3-D NAND, spin torque transfer MRAM, ferroelectric memories, and other emerging memory types. Intel’s K. Zhang will give an invited paper on SRAMs using tri-gate transistors, scheduled for June 13th in the late morning

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We have all heard that planar transistors have run out of steam. There are two ways forward. The one that has garnered all the attention is Intel's trigate which is their name for FinFET. The other is using thin film SoI which ST is doing. TSMC and Global seem to be going the FinFET way too, although at a more leisurely pace. But why are planar transistors running out of steam? And why are these the two promising ways forward? Dr Chenmin Hu, the inventor of the FinFET first described in a 1999 paper (pdf), gave us all a tutorial. It was fascinating. I thought that most of the power of the FinFET came because the gate wraps around the channel on three sides and three is better than one. But that is not the real story

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Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics at University of California at Berkeley gave a keynote talk on FinFETs and FDSOI (fully depleted silicon on insulator) today at the GSA Silicon Summit held at the Computer History Museum in … Continue reading →

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EL SEGUNDO, USA: Solid manufacturing and strong pricing allowed Micron Technology Inc. and Hynix Semiconductor Inc. to post strong performances in the global NAND flash business in the fourth quarter, allowing them to narrow the gap in market share between them and the industry leaders, and setting the stage for further advances in 2012. No. 3-ranked Micron ... GLOBALFOUNDRIES Fab 8 adds tools to enable 3D chip... IR to showcase automotive power

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There is an interesting discussion in the SemiWiki forum in response to the EETimes article: Intel exec says fabless model 'collapsing'. Definitely an interesting debate, one worth our time since the advertising click hungry industry pundits will certainly jump all over it. Clearly I’m biased since I helped build the semiconductor ecosystem. I will certainly try and be open minded here, but probably not

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Silicon wafer maker Soitec S.A. claims that chip makers can sidestep years of development work needed to perfect fully-depleted (FD) silicon transistors by switching to its silicon-on-insulator (SOI) wafers, a ploy that has already convinced STMicroelectronics NV, ST-Erikson and IBM Corp. to give it a try.

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In an effort to gain a stronger foothold in the coming fully depleted CMOS era, Soitec (Bernin, France) said it is ready to provide silicon-on-insulator (SOI) wafers to both planar (FD-2D) and finFET (FD-3D) customers

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A few weeks ago, I came across an article on a new nanotechnology process in development at Rice University that can be used to build transparent, flexible 3D memory chips. According to the article, these chips could replace flash memory in thumb drives, smart phones and computers. The transparency also makes it perfect for touchscreen displays, and such futuristic concepts as smart glass for windshields that could then have functionality built into something that previously just served the purpose of optics. Really, the possibilities appear to be endless. Of course, the 3D aspect of the technology is what caught my eye, so I contacted James Tour, Ph.D, the synthetic organic chemist at Rice who is responsible for this technology, to get more details such as how these chips are manufactured, how far along in the development it is, and how it measures up cost-wise to current technologies – stuff like that

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So we see that NAND scaling is going to keep going for a few more generations. And the innovations and process manufacturing technologies and the kind of vertical integration that you heard about earlier from Sanjay and

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Professor Tim Cheng adn Dimitri Strukov at the University of California at Santa Barbara described how 3-D techniques could realize the dream of semiconductor memristors.

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In this paper, we give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. These hybrid circuits combine a CMOS subsystem with several layers of nanowire crossbars

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Have you read some of the recent TSV headlines? 1. January 31, 2012 - CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects.

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Recently I read a very uncommon report title: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless". Quoting directly: “One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or NVIDIA admit to manufacturing problems... That’s why we were surprised - and our source testified to being stunned - that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November”

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Most experts believe that silicon scaling will end by 2020 at the 10 nanometer node. Although several promising post-CMOS technologies, such as graphene or III-V compound semiconductors or even spintronics might take its place, these technologies will not be deployed before 2025 at the earliest. But if the industry were to adopt and perfect 3d technology, the industry might eventually create chips with hundreds of layers. The most common form of 3d technology involves through silicon vias, but a startup company called Monolithic 3d has an alternate approach. In an interview with Sander Olson for Next Big Future, Monolithic CEO Zvi Or-Bach argues that monolithic 3d is a viable, cost-effective technology that could keep Moore's law going until 2030.

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First rumors about the demise of flash surfaces as early as 2004 when there was speculation that MRAM, OUM, PRAM or nanocrystal-supported flash would replace flash memory chips beyond the 32 nm scale by 2009. Despite the fact that flash is still going strong even in 2012, researchers believe they have identified a new technology that will replace flash someday: Transparent, flexible 3D memory chips

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Applied Materials Inc. (AMAT) is the leading supplier of semiconductor fabrication fab equipment to the global semiconductor industry. After Applied Materials' (AMAT) Analyst Day this week, Citi, Barclays Capital, and Credit Suisse share their bullet-point takeaways about the semiconductor and related manufacturing industries, gleaned from Applied's presentations:

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New memory chips that are transparent, flexible enough to be folded like a sheet of paper, shrug off 1,000-degree Fahrenheit temperatures, and survive radiation could usher in the development of next-generation flash-competitive memory says Dr. James M. Tour, Professor of Computer Science, Mechanical Engineering, and Materials Science at Rice University

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The 2.5D/3D chip era continues to gain momentum, as Altera Corp. this week made a major announcement in the arena. Indeed, the advent of 2.5D/3D chips based on through-silicon vias (TSVs) is considered a “game changer” in the semiconductor market, but mass production for the technology is still a moving target

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Mark Bohr, senior fellow and director of Intel’s process architecture and integration, sat down with Semiconductor Manufacturing & Design to talk about his company’s push into Tri-Gate, its future SoC direction and what will drive chip design and manufacturing in the future. What follows are excerpts of that conversation.

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During lunch there is a 3D IC panel moderated by Steve Leibson of Cadence: Herb Reiter; Samta Bansal of Cadence; Dusan Petranovic of Mentor; Deepak Sekar of Monolithic 3D; Steve Smith of Synopsys. Recommendations

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Memcon 2012 will take place at the Santa Clara Convention Center in the heart of Silicon Valley on Tuesday, September 2012. This is the biggest conference in the world devoted to the use and manufacture of semiconductor memory (RAM, NAND … Continue reading →

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... Study with Monolithic 3D Integration; Cost-minimized Double Die DRAM Packaging for Ultra-High Performance DDR3 and DDR4 Multi-Rank Server DIMMs; Advanced Analysis and Characterization for Sub-Micron Design

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EL SEGUNDO, USA: With its leading market share position and high memory usage, Apple Inc.'s iPad is set to continue to dominate worldwide demand for NAND flash in media tablets at least through the year 2015, according to the IHS iSuppli Memory & Storage Service. Apple's iPad in 2011 accounted for a commanding 78 percent of global .... ECT's world's first 3D chip supporting MIPI employ... GigOptix ramps new 28Gbps modulator GX6262 driver ... GaN power

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or the most part, the DRAM and NAND flash industries have been having a hard time, especially in terms of oversupply and pricing pressures. Shaky at best, the markets' foundations have been constantly struggling even at the slightest movement in the market. Looking into the future of the two segments, DRAMeXchange, a research unit of TrendForce Corp., has predicted six upcoming market trends for the industries from 2012-2015

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The 1999 IDM paper Sub 50-nm FinFET: PMOS started the 3D transistor ball rolling, then in May of 2011 Intel announced a production version of a 3D transistor (TriGate) technology at 22nm. Intel is the leader in semiconductor process technologies so you can be sure that others will follow. Intel has a nice "History of the Transistor" backgrounder in case you are interested. Probably the most comprehensive article on the subject was just published by IEEE Spectrum “Transistor Wars: Rival architectures face off in a bid to keep Moore's Law alive”. This is a must read for all of us semiconductor transistor laymen.

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about "Chip 2020" book review.

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We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about the semiconductor equipment manufacturing: "Who wins from the recent consolidation?"

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We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about the semiconductor equipment manufacturing: "Who wins from the recent consolidation?"

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It may seem strange to link two interchip interface standards to the future of3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design SoCs in the near future

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In much the same way that Intel has moved to FinFET to scale beyond 22nm, 3D-ReRAM is expected to take over from NAND flash at around 11nm, sometime in the next few years. It is anticipated that 3D-ReRAM will be so

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(See “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron” and “The End of NAND Flash as we Know It: Micron's Dean Klein and Samsung's Tony Kim Look at Life After Flash”). Micron 3D NAND Flash

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Deepak Sekar, Chief Scientist at MonolithIC 3D, has just published a provocative blog with big implications for both the semiconductor memory and foundry businesses. His premise is that even though Samsung has “only”

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Samsung contributes just 7% to the world’s foundry revenue today. But here’s why it could be TSMC’s biggest challenge yet...

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Wafer-level packaging and 3D NAND are two market drivers that will propel revenues at the combined Lam-Novellus operation this year and next, chief operating officer Tim Archer said

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Several years ago, an executive from Intel Corp. declared that flash memory would run out of gas and would stop scaling at about 90nm, prompting the need for a next-generation — or universal — memory type. FRAM, MRAM, phase-change, ReRAM and others fall into the so-called universal memory category. Developers of these technologies claim their respective technologies can replace DRAM, NAND, NOR — or all three

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I recently saw this great 5 minute video by Applied Material’s Richard Lewington [AMAT 3D Blog Video] where three types of 3D-IC construction are demonstrated. Note that the first two 3D-IC options he shows (with those plastic blocks) are monolithic. Only the third option is TSV based

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One of the commonly quoted challenges for wafer-level 3D-IC stacking is yield. ... MonolithIC 3D Inc. claims its yield repair scheme could allow excellent yields for 3D-ICs constructed with dozens of stacked wafers. In addition

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Ever since I put on the editorial director hat for 3D-ICs.com, which aggregates 3D technology news, blogs and papers, and categorizes them as either TSV and 3D packaging or monolithic 3D, I’ve been trying to wrap my head around the differences between 3D TSVs and monolithic 3D integration technologies. I’ve got 2.5 D and 3D TSVs down pat, but the monolithic thing was really eluding me. I decided the best course of action was to tap into an expert in the monolithic realm. Who better to talk to than Zvi Or-Bach, CEO of MonilithIC 3D? I figured if his company carries the technology name, he must know the most about it. I wasn’t disappointed. Or-Bach graciously explained it all to me, right down to the fundamentals. Now that I’ve got it all straightened out, I figured 3D InCites readers could benefit from this knowledge as well

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Today, we'll discuss why TSV pitches smaller than 500nm are useful and how one can achieve that. Evolutionary advances with today's TSV technology as well as radically new monolithic 3D approaches are options. The Silicon Valley IEEE Components, Packaging and Manufacturing Technology (CPMT) Society invited me to give a talk on "Fine-Grain 3D Integration" last wee [...]

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Picture We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses yield and repair issues with 3D stacked chips

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Novellus Systems CEO Rick Hill, in what may be one of his last public appearances in that role, said orders for semiconductor equipment are strengthening and 2012 may turn out to be much better than prognosticators are forecasting. Speaking early Thursday (Jan. 12) at the Needham Growth Conference for investors, Hill said “the force fields are in place” for 2012 to be “flat to slightly up” in terms of semiconductor equipment revenues

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The might have beens. The shoulda's, coulda's, woulda's are what launches a thousand Harvard Business School Case Studies that are meant to prepare a generation of business leaders on how to make decisions that impact the future directions of companies. Right before the 2008 financial crises (September 5, 2008), Samsung made a run at Sandisk in order to reduce its NAND Flash royalty payments. A year later, Sandisk rejected Samsung’s final offer for what would be half the value of the company today. Samsung can look back and say that was a big fork in the road and hopefully for them it wasn’t a “stick a fork in it” moment.

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MonolithIC 3D Inc., a leading 3D-IC company, announced its Ultra-Scale Integration scheme last week. ThMonolithIC 3D Inc., a leading 3D-IC company, announced its 3D NAND flash memory technology yesterday. The technology, interestingly, uses monocrystalline silicon for transistors in contrast to the polysilicon approaches of companies such as Toshiba, Samsung, Hynix and Micron. Considering that monocrystalline silicon offers 3x-6x higher mobility and dramatically lower variability compared to polysilicon, the quality of memory cells is expected to be significantly better.

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Joe Sawicki is the VP and General Manager at Mentor Graphics for the Design-to-Silicon Division where the Calibre product line is developed. We met today in Wilsonville, Oregon to review the challenges in IC design, processing and manufacturing

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Toshiba, Samsung, Hynix and Micron have aggressively invested in monolithic 3D technologies, and impressive progress is being made with every passing day. Dr. Deepak Sekar, the Chief Scientist of MonolithIC 3D Inc.,

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi introduces a very interesting idea that could have huge implications for high-performance computing

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Toshiba, Samsung, Hynix and Micron are developing polysilicon-based monolithic 3D flash memories. Today, I’ll talk about these and also introduce our company's monocrystalline silicon solution

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We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses the foundry industry's history as well as its current landscape

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Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn’t get to in the first two posts, which I’ll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory technologies, specifically ReRAM

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Sekar is MonolithIC 3D's Chief Scientist, so I suppose I should also sport those credentials to wade in here with Sekar and Dally, but as they say, fools rush in where angels fear to tread. So here goes. Sekar's latest blog entry

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Over the years, NAND flash vendors have leapfrogged each another for the process technology lead in the arena. Most recently, the Intel-Micron duo were the leaders in April, when the two NAND manufacturing venture partners rolled out a 20nm process technology and the associated 20nm parts. Intel Corp. and Micron Technology Inc. have a joint NAND manufacturing venture, dubbed IM Flash Technologies LLC (IMFT)

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I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how Korea became the De-facto memory hub. The story of Korea in the 1960s and where India

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Bill Dally, Chief Scientist of nVIDIA and Professor at Stanford University, gave a great keynote speech on the future of computing recently. Let's discuss his presentation today...

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The industry’s current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D tool flows, thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D design. A new 3D design process is evolving gradually from that 2D heritage. When Tezzaron designed its first 3D circuits in 2003, the designers used standard 2D CAD tools and cobbled together a 3D DRC and LVS flow based on scripts. Today there are tools to handle a complete backend flow and strides are being made to enable true 3D design partitioning, synthesis, placement, and routing (see Figure 1)

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As you'd know, Korean companies such as Samsung and Hynix contribute 50-60% of the world's memory revenues. In today's blog post, we’ll look at reasons and strategies behind this dominance...

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We have a guest contribution today from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses Monolithic 3D's potential impact on the semiconductor industry... Recently EE Times quoted Shang-Yi Chiang, senior vice president of R&D at TSMC: "The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node". Yet, at the time, EE Times quoted Chi-Ping Hsu, senior vice president at Cadence: “Process R&D, for instance, jumped from $1.2 billion at 32/28nm to between $2.1 billion and $3 billion at 22/20nm". So clearly the “clear path” is associated with escalating costs

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My last panelist, Zvi Or-Bach, is President and CEO at MonolithIC 3D, is a serial semiconductor entrepreneur. He’s not content with the benefits of 2.5D and 3D assembly. His company is shooting for true 3D IC manufacturing.

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The industry’s current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D tool flows, thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D design. A new 3D design process is evolving gradually from that 2D heritage

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Ever since the TSMC OIP Forum where Dr. Shang-Yi Chiang openly asked customers, “When do you want 3D Transistors (FinFETS)?” I have heard quite a few debates on the topic inside the top fabless semiconductor companies. The bottom line, in my expert opinion, is that TSMC will add FinFETS to the N20 (20nm) process node in parallel with planar transistors and here are the reasons why:

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Sometimes we get questions about a particular aspect of the monolithic 3DIC flow. In this blog I would like to talk about Low Temperature Wafer Direct Bonding, where an important concern is the strength of the wafer to wafer

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We have a blog post today from Ze'ev Wurman, the Chief Software Architect of MonolithIC 3D Inc. Ze'ev spent many years leading EDA/software work at Dynachip, eASIC and Amdahl. He will discuss CAD tools for 3D-ICs. With so many people talking about 3D chips, it’s time to focus on the CAD tool support for them. I find it easiest to look over the CAD landscape using two distinct views.

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It is commonly believed that the fundamental limit to MOSFET feature-size scaling is direct source-drain tunneling. We may hit this limitation around the 5nm node.

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It is commonly believed that the fundamental limit to MOSFET feature-size scaling is direct source-drain tunneling. We may hit this limitation around the 5nm node. Is that the end of the road for CMOS Scaling? Last week, during a dinner conversation with colleagues, the topic of scaling limits came up. Hmmm... I thought. Let me study this issue

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Rival architectures face off in a bid to keep Moore's Law alive

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Believe it or not, the answer is True! Who did it? It was Matrix Semiconductor, a Silicon Valley startup, who shipped the world's first monolithic 3D products in 2003. These were One-Time Programmable (OTP) non-volatile memory chips that had multiple layers of polysilicon diodes in series with antifuses. See picture alongside

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Picture We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology. Brian shares his perspective on Low Temperature Wafer Direct Bonding, where an important concern is the strength of the wafer to wafer oxide to oxide bond

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Furthermore, moving to recessed channel devices could enable easy implementation of Monolithic 3D-ICs. See this page ... The NAND flash industry has monolithic 3D on their roadmap in the next 2-3 years. If you liked this

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Last week, the industry was abuzz with news of Hynix's 15nm NAND flash memory technology. This important milestone brings our industry into the quad patterning era. I'll talk about quad patterning and its implications today

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We have a guest contribution today from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. In this post, Zvi shares his perspective on where the industry is going after attending the recent Future Horizons conference (IEF-2011)

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Deepak Sekar, Chief Scientist of MonolithIC 3D Inc, published a blog about power distribution in 3D ICs way back in March but a recent discussion post on LinkedIn has highlighted it once again. Sekar writes about several ways to approach the problem of distributing power on 3D ICs but perhaps the last two sentences in his post is the one to read first:

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hrough-silicon via (TSV) on chip interconnection of memory, processor and sensor elements looks the most likely route for 3D chip design, writes Richard Wilson

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We all hear "Timing is Everything", and it is so very true for a startup - too early could be as bad as too late. Being an entrepreneur, I am probably far too optimistic to present an objective view and especially with respect to the Monolithic 3D-IC. So you could be the judge and hopefully reality will soon provide the final judgment.

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The 3D DRAM race is heating up, as more companies are teaming up to share the costs and accelerate the development of the technology. Last week, two memory rivals — Micron and Samsung — formed an alliance to devise 3D DRAMs using a stacked through-silicon-via (TSV) technology. Another 3D DRAM alliance — which includes Elpida, Powertech and UMC — last week revealed more details about its strategy. And recently, Hynix formed a 3D DRAM partnership with Sematech

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To listen to John Lau, of ITRI, speak on the topic of 3D integration is to experience a passion for technology that rivals no other; except perhaps that of Rao Tummala of Georgia Tech. But John is definitely more vocal in his passion. Rao has a softer, gentler approach. At this year’s IWLPC in Santa Clara, both expressed their perspectives on what they see as the most cost effective and immediately available path to achieving 3D integration using passive TSV interposers as either substrates or carriers

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Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a “killer app” for 3D IC assembly. Last week, founding members Micron and Samsung announced the Hybrid Memory Cube Consortium (HMCC) dedicated to expanding “the capabilities of the next generation of memory-based solutions.” Current “Developer Member” companies include Altera, Micron, Open-Silicon, Samsung, and Xilinx

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Home > ADVANCED PACKAGING: 3D IC, WLP & TSV > The Intel “Tri-Gate Transistor” structure: a closer look... > ADVANCED PACKAGING: 3D IC, WLP & TSV. Oct 4th, 2011. The Intel “Tri-Gate Transistor” structure: a closer look. At the most

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Guest blogger Ze'ev Wurman, an executive with Monolithic 3D, a Silicon Valley startup, has participated in developing California's education standards and assessments in mathematics since the mid-1990s. Between 2007

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D NAND has the potential and the promise to supplant 2D planar NAND. Whether it will or not remains to be seen. Challenges remain leading up to commercialization. But the race is certainly on. Equipment makers, such as Novellus, are saying that 3D NAND pilot lines will likely be up and running in 2013 and if all goes well volume production will commence a year later in 2014

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There is a big difference between TSV type 3D IC and what I am talking about – monolithic 3D (10000x vertical connectivity)! With monolithic 3D IC every folding is equivalent for 1 node of scaling from every point one look at.

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MonolithIC 3D Inc., a Silicon Valley company, says the framework does not call for using analytical mathematics such as algebra, trigonometry and calculus for studying science problems. Mathematical concepts are the

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... to achieve higher levels of manufacturing efficiency for such applications as backside illuminated (BSI) CMOS image sensors, 3D integration of CMOS image sensors, and monolithic 3D integration of memory devices.

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It’s time to think vertically. Geometry shrinks are slowing down and its getting harder and harder to shift to the next process node with each jump. The answer is 3D NAND. We need to break through into another dimension

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With deployment in some 5 billion mobile devices worldwide, flash memory has been wildly successful. But where will nonvolatile memory technology go from here, and how much further can it scale? Some answers emerged from three keynote speeches at the Flash Memory Summit August 9

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NAND as we know it is reaching the end of the line. It’s been a good run. But Judgement Day is Coming!

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Deepak Sekar, Chief Scientist of MonolithIC 3D, has just published a really interesting blog post with a somewhat cryptic title, in my opinion. The title of the post is “Can 450mm Decommoditize the Semiconductor Industry?

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We're hitting a memory wall, if you didn't know, and processor cores are going to be held up because DRAM can't scale up enough or ship 'em data fast enough. Samsung and Micron aim to fix that with 3D memory cubes and a consortium to define an interface spec for them

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The next International Interconnect Technology Conference (IITC 2012) will be held in San Jose in a couple of weeks (June 4-6). This is a good opportunity to recall that, in some sense, the reason for scaling silicon down has changed in recent years from packing more transistors in a square (or cubic) millimeter to increasing functionality and performance at reduced power. An ever higher fraction of the power dissipation resides in the interconnect – both in the net switching itself as well as in the ever-increasing number of repeaters required to re-power more and more “long” nets

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